These are the release notes planned to go out with the 25.06 release.
Note that we've removed the bugs section. We may look at adding
"Fixed Bugs" and "New Bugs" in the future, but it was depressing not
seeing changes between the releases.
Change-Id: I8cedbdb7b05605d1904446590fb25552a7e0c727
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88206
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add FW_CONFIG probe based on pujjolo boxster of below devices:
Mipi camera
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify the mipi camera device are set based on
fw_config.
Change-Id: I8760585d5012073fb3ca1d2636474a07b8eea97a
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
1. This change is based on the fact that the code for the pujjolo
and pujjoquince projects is shared.
2. Add fingerprint function and use proto board to verify the
functionality.
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:395763555
BRANCH=none
TEST=Use ectool --name=cros_fp version will return fingerprint
version information and check the functionality works.
Change-Id: I557c7b6a10b137604ff4abae81c7a231c48b099d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88186
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current QCOM fixup function qualcomm_find_hash() assumes only one
ELF will be loaded by the primary boot loader and the bootblock is one
of the segments of that ELF.
However, the primary boot loader for QCOM X1P42100 SoC loads multiple
ELFs for QC_SEC, TME Sequencer, TME FW and bootblock. This change
updates the fixup functionality to handle bootblock being a separate
ELF.
If the bootblock offset does not fit within the first ELF, then the
fixup function understands that it is a multi ELF.
Additionally, it ensures the bootblock ELF uses MBN v7 format.
BUG=b:420542130
TEST=1. Create a image.serial.bin and ensure it boots on X1P42100
2. Used the following script to verify the hash
#! /bin/bash
image=/build/bluey/firmware/image-bluey.serial.bin
bin=/tmp/bb.bin
seg=/tmp/bb.seg
hash=/tmp/bb.hash
#
# Bootblock is the final ELF of the multi ELF. Hopefully
# there is no other ELF in ${image}. Get the offset of the
# final ELF in ${image} and get it out
#
bb_offset=`od -Ad -w4 -tx4 ${image} | grep 464c457f | tail -1 | cut -f1 -d ' '`
dd if=${image} of=${bin} skip=1 bs=${bb_offset} &> /dev/null
#
# The last two segments of the bootblock ELF have the actual
# executable and the hash. 'LOAD' is the executable segment and
# the other is the hash segment. Get their offsets and convert
# to decimal.
#
offs=`readelf -lW ${bin} | tail -2 | awk '{print $1" "$2" "$5}'`
offs=(`printf "%s %u %u %s %u %u" ${offs}`)
#
# Get the executable and hash segments
#
if [ ${offs[0]} = "LOAD" ]; then
first=${seg}
second=${hash}
else
first=${hash}
second=${seg}
fi
dd if=${bin} skip=${offs[1]} bs=1 count=${offs[2]} of=${first} &> /dev/null
dd if=${bin} skip=${offs[4]} bs=1 count=${offs[5]} of=${second} &> /dev/null
#
# Find the SHA384 hash for the executable segment
#
sha=`sha384sum ${seg} | cut -f1 -d ' ' | sed 's/../& /g'`
echo ===================================================
echo Expected hash:
echo
echo ${sha} | fold -w48
echo ===================================================
echo
hexdump -C ${hash} | grep -A4 "`echo ${sha} | cut -f1-4 -d ' '`"
Change-Id: If57ba0cc9a4f08b69d7712f27c215339307e73d4
Signed-off-by: Varadarajan Narayanan <vnarayan@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88148
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PBL of QCOM X1P42100 SoC loads image in multi ELF format, which is
a concatenation of TME SEQ, TME FW, QC-SEC and Bootblock binaries.
This script stitches the binaries together into multi ELF image.
Usage: create_multielf.py [-h] -f IN_FILES [-o [OUT_FILE]]
Example: python create_multielf.py -f image1,image2,image3 -o output.bin
Change-Id: I9cdbdf6b5c62663491ccd7d42ab270742760aa0b
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88145
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
1. This change is based on the fact that the code for the pujjolo
and pujjoquince projects is shared.
2. Add SD card function and use proto board to verify the
functionality.
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify the mmcblk0 shown which use lsblk
command, and check if sd card could store file in desktop.
Change-Id: Ib7f854d9c902ba3f257d154ae6b95ea443fa78f5
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88184
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This new variant will support PTL pre-production silicon. The existing
`fatcatite` variant will support production silicon.
BUG=b:424355826
TEST=Able to build google/fatcatite4es.
Change-Id: I9c51c1720a354f80edcf8c8ef75bd564dd6a5b5d
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88128
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This new variant will support PTL pre-production silicon. The existing
`fatcatnuvo` variant will support production silicon.
BUG=b:424355826
TEST=Able to build google/fatcatnuvo4es.
Change-Id: I079f9bbf0be9c3149b3f583102bec32f328ab44d
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88129
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This new variant created will support PTL pre-production silicon. The
existing `fatcat` variant will support production silicon.
BUG=b:424355826
TEST=Able to build google/fatcat4es.
Change-Id: I0f925a73a42aaf6d3ae6980169d912374b12d8ae
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces support for the H58G66BK7BX067 memory module
within the Intel PTLRVP mainboard variant. The changes include updates
to several configuration files to recognize and utilize this specific
memory module. The SPD source files and DRAM ID assignments have been
updated accordingly to integrate the new memory module into the build
system. This addition ensures compatibility and functionality with
the H58G66BK7BX067 memory module, allowing for expanded hardware
support and flexibility in memory configurations.
BUG=none
TEST=Build and verify memory module detection and initialization
on supported hardware configuration.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ic281125dd40bbcef50d138e912e7557d6552eb9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88177
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the focaltech
touchscreen (FTSC1000) device, connected to I2C bus 38.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
Datasheet: FT8112_Data_Sheet_V0.2_HKC20240415.pdf
BUG=b:426038745
TEST=emerge-nissa coreboot and focaltech touchscreen can work well.
Change-Id: I478924fbebf2a5ecd60bad48b37bfa6581100601
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This reverts commit 2e495b09d5.
Reason for revert: mmio_tseg is reserved twice in
mc_add_dram_resources, where the duplication is introduced by
commit 43b0ed7089 ("soc/intel/xeon_sp: Improve final MTRR solution")
Change-Id: I0f1bf757d8d1fc449e4efc0ec171c6f982f79e9e
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add support for the new memory CXMT CXDB4CBAM-ML-A.
BUG=b:427090130
TEST=Use part_id_gen to generate related settings
Change-Id: I176fb49c17379fcf454f5a4d3ab4b057b50d34ce
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88167
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New Touchscreen function for Quandiso project.
Touchscreen panel: HKO RB116AS01-4
Datasheet : Product%20Spec_RB116AS01-4_ver1.0.pdf
BUG=b:424332291
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Confirm command evtest and touchscreen function is workable.
Change-Id: I6b1f9929fc63c056d7714c9ed67bcaffeebdab8b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
It causes some name clashes (and therefore overshadowing) of function
names defined in xeon SOC code in later patches of the patch train.
We don't really have a standard naming scheme for callback functions, so
I just added a _func suffix/postfix to indicate the function is a
callback function and to prevent name clashes.
Change-Id: I21811f75ef6e7642a7e4f69997737cd7b8b1cef9
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
get_oled_description is a wrong function declaration. Remove
get_oled_description function declaration and include soc/display.h
for get_active_panel.
Change-Id: Id321882d5b4b00f4114ef7282d13af9003019f62
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88139
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SoCs with dptx_v2 (such as MT8196) use a different eDP MAC design from
old SoCs with dptx_v1. The formulas for register calculation are
different:
- The horizontal blanking (REG_3160_DP_ENCODER0_P0) is hsync + hbp + hfp
on MT8196, while on older SoCs it is hsync + hbp.
- The vertical blanking (REG_3174_DP_ENCODER0_P0) is vsync + vbp + vfp
on MT8196, but vsync + vbp on earlier SoCs.
The current formula for MT8196 only works correctly when ha/va are
multiples of 4 and hfp/vfp are 0. The new formula fixes display errors
at resolutions like 1366x768 (ha=1366, hfp=48).
To distinguish these differences, an edp_version parameter is added.
Also update the following settings for correct configuration:
- Set AUX_RX_UI_CNT_THR_AUX_FOR_26M to 14 to correct the previous
incorrect setting.
- Fix DVO_TGEN_H1 calculation for the case where ha is not a multiple
of 4 (such as 1366).
BUG=b:400886838
BRANCH=rauru
TEST=Check the display function on Navi
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Id0ae6845ce6a06cdcbc3dd9b1f8a63e2890c3b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88188
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The Ocelot variants must support ES silicon as well as QS silicon. This
CL changes ocelot to ocelot4es, changes ocelotite to ocelotite4es, and
changes ocelotmchp to ocelotmchp4es.
BUG=b:425397790
TEST=`emerge-ocelot` and verify it builds without errors.
Change-Id: Iac0700688e7f616477bf462c5734a70110f9d6d7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88134
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add panel driver in mainboard for skywalker project.
BUG=b:400886838,b:425272330
BRANCH=none
TEST=check edp training pass and show log:
EQ training pass
Change-Id: I7352a6728237842a6819b7129c61a1d4c7646fcb
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88170
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the dptx_v2 common driver, add eDP driver to adjust training
flow and turn off PHY power before PHY configuration to prevent
potential link training failures. Also correct the DISP_DVO0 address
since the initial value is not thoroughly checked during early bring-up.
DISP_DVO is a highly advanced variant of DP_INTF block for eDP or HDMI
or simply digital video output. DISP represents "display", while DVO is
the abbreviation of "digital video output". This version of DISP_DVO is
mainly designed for eDP1.5 protocol.
BUG=b:400886838,b:422095960
BRANCH=none
TEST=Check the display function on Skywalker. Check the log for
"EQ training pass".
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I59cfdae1d13cf7fb9627a4d534602cb309df3d67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88168
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
According to the eMMC specification, the maximum allowed source clock
frequency is 200MHz. Currently, a 416MHz source clock is used, which
after division results in 208MHz. This exceeds the spec limit.
Additionally, considering possible frequency fluctuations and desense
issues, 384MHz is a more reasonable and safer value. Limit the source
clock frequency to 384MHz to ensure compliance with the eMMC
specification and improve system stability.
BUG=b:396258620
BRANCH=none
TEST=echo fmeter > /proc/clkdbg ; cat /proc/clkdbg |grep msdcpll
30: fm_msdcpll_ck : 383500
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.corp-partner.google.com>
Change-Id: I3c704b1200dd89a05476a5b14b75950aead51f30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Meliks uses panel-built-in touch screen, it needs to set panel power
and reset signal to high for touch screen to work.
On user mode, coreboot doesn't initialize graphics since there is no
screen display before OS. So we would add a WA to initialize required
signals on user mode. It takes under 30 ms delay on booting time.
Bugzzy has fixed the same issue, copied the WA code from bugzzy.
- 1106bcce0d: `bugzzy: Initialize display signals on user mode`
Reference: HX83121-A panel specification (Page 60 - 64):
https://drive.google.com/file/d/1Q0wjzHmSOa_r2FwiNe4PtKWmhhacBw4W/view?pli=1&resourcekey=0-pnGgp8yzf68UpyqNE1Caew
BUG=b:412584604, b:398703068
BRANCH=nissa
TEST=Verified touch screen worked with test coreboot without FW splash
screen. (crrev/c/6647126)
- A part of `cbmem -t` result before this change:
```
115:finished elog init 914,227 (2,679)
70:device setup done 915,121 (893)
...
1101:jumping to kernel 1,055,074 (9,849)
Total Time: 1,055,039
```
- A part of `cbmem -t` result after this change:
```
115:finished elog init 911,708 (2,674)
70:device setup done 936,680 (24,971)
...
1101:jumping to kernel 1,073,415 (9,360)
Total Time: 1,073,379
```
Change-Id: I92c7754cfbdf73e84a25b6d45b062ba9cafb04ab
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88107
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Applies a `logo_bottom_margin` of 100 pixels to the `common_soc_config`
for the Fatcat mainboard and its variants (Felino, Francka, Kinmen).
This configures the OEM footer logo to be rendered 100 pixels above
the bottom edge of the screen.
BUG=b:423591644
TEST=Verified OEM footer logo displays 100px above the bottom edge on
google/fatcat builds.
Change-Id: I30a63b6ecccd20380d7f0b402891e286967284c3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Introduces logo_bottom_margin to soc_intel_common_config to allow
adjusting the vertical (or horizontal, based on orientation) offset of
the footer logo from the screen edge. This provides flexibility for
OEM branding placement.
BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat.
Change-Id: Ie3942d9eee07091286118ac488d1cc85ecc96c4c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Many high-capacity SPI flashes (e.g., >16MB) default to 3-byte
addressing and require a specific command to enter 4-byte address mode.
This commit introduces support for sending the
CMD_FORCE_4BYTE_ADDR_MODE (0xB7) command during flash probing. When
Kconfig option `SPI_FLASH_FORCE_4_BYTE_ADDR_MODE` is enabled, this
ensures the flash chip is immediately switched to 4-byte addressing
after power-on.
This addresses issues with flashes like GigaDevice (GD25LQ128D) and
Winbond (W25Q256JWxx) that mandate this command for proper 4-byte
addressing. The new command definition is in `spi_flash_internal.h`.
BUG=b:417900125
TEST=Able to build google/bluey.
Change-Id: I935a0e1d6214d73c8ea487418adc93f016790432
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88156
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 0e5d1d29bd ("soc/intel/skylake: Expand USB OC pins enum to
OC7") added the missing OC6 and OC7 enums for PCH-H, so use those
instead of a bare integer to map USB2 ports 10 and 11 to overcurrent
pin 6.
TEST=Timeless build did not change
Change-Id: I3680fae39e96783e4434b36a8dfd751888541cbb
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
For "basic" (initial) memory training, we use larger-than-usual timings
for a few things, namely tCMD and tXP. After basic training is done, we
can switch to the final timings for the training steps that follow (not
many at the moment). Without this, NRI keeps using the training timings
at all times, which results in slightly lower performance (likely to go
unnoticed unless benchmarking the system).
Tested on Asrock B85M Pro4, still boots to Arch Linux.
Change-Id: I625f35adb02b36b1087cd758f983118d0a60b815
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Currently, the overcurrent pin enum is only defined up to OC5. However,
PCH-H chips support up to OC7 according to the 100 and 200 Series PCH
datasheets [1][2].
[1] Intel document 332690
[2] Intel document 335192
Change-Id: Ie35612eeaed2196caccc514429c7d80f84cf09a8
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88159
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the kaladin variant of trulo reference board by copying the
template files to a new directory named for the variant.
Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.
BUG=b:420836320
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KALADIN
Change-Id: Ib0cbe8c4c0d988aec1bab0f272d1abd532cbc54f
Signed-off-by: wu.garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Add ChangXin CXDB4CBAM-ML-A as id 2, resulting in the list below:
DRAM Part Name ID to assign
K4U6E3S4AB-MGCL 0 (0000)
K4UBE3D4AB-MGCL 1 (0001)
MT53E1G32D2NP-046 WT:B 1 (0001)
NT6AP512T32BL-J1 2 (0010)
NT6AP1024F32BL-J1 3 (0011)
CXDB4CBAM-ML-A 2 (0010)
BUG=422906387
TEST=Use part_id_gen to generate related settings
Change-Id: Ia9c091975cca6442833d374d40e98299ed5f0f0d
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
According to the latest SPD parameters provided by the manufacturer,
combined with the document 8Gb_LPDDR4X_B_Die_component_Datasheet(S).pdf
we correct channelsPerDie, diesPerPackage, ranksPerChannel of SPD
for Nanya NT6AP1024F32BL-J1; merged the parameters into the BIOS and
flashed it into the machine. The machine can boot and read the normal
size of memory.
BUG=b.422906387
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
Use the dmidecode -t memory command to read the size of memory.
Output results：
awasuki-rev2 # dmidecode -t memory
# dmidecode 3.4
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x000A, DMI type 16, 23 bytes
Physical Memory Array
Location: System Board Or Motherboard
Use: System Memory
Error Correction Type: None
Maximum Capacity: 64 GB
Error Information Handle: Not Provided
Number Of Devices: 4
Handle 0x000B, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 32 bits
Data Width: 32 bits
Size: 8 GB
Form Factor: Unknown
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: LPDDR4
Type Detail: Synchronous
Speed: 2933 MT/s
Manufacturer: Unknown (b03)
Serial Number: 00000000
Asset Tag: Not Specified
Part Number: NT6AP1024F32BL-J1
Rank: 2
Configured Memory Speed: 2933 MT/s
Minimum Voltage: 0.6 V
Maximum Voltage: 0.6 V
Configured Voltage: 0.6 V
Change-Id: I35823ce87b5d8d67894528e4a8781dd91247eb6c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88146
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current approach has two problems:
- Just because the source address is 0 does not mean it is no
specifically set. A bunch of mainboards specify their APOB_NV base
address at 0 in their FMAP files.
- There is no AMD SOC that has support for this binary, but doesn't give
AMDFWTOOL the base address. It would also not work considering that
AMD common/block/apob code gets the region from the FMAP.
Therefore just remove the check since no mainboard will ever enter the
else branch.
tested: binary identical for at least 1 mainboard on each SOC
generation.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic85d6b25c95ab12dbcc72d17158591891dd04e97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add ACPI ASL code for the discrete NVIDIA GN21 GPU. Based on
google/brya, but adapted for Meteor Lake and the specific GPU found in
Clevo V5x0TNx.
NVIDIA did not provide us with the required documentation, so this
driver is entirely based on the Brya implementation, and poking Clevo
ACPI from Linux.
Without this patch, the NVIDIA driver would not load at all under
Windows, while Ubuntu would load the driver, but would be unable to
power off the dGPU, causing increased power draw.
TEST=Boot to Windows 11 via MrChromebox uefipayload_2502 and observe
that the NVIDIA Driver loads correctly, that the dGPU powers off when
unused and powers on while needed. Do the same in Ubuntu 24.04 under a
Gnome X11 session.
Change-Id: I9e5715cb4129a005cc9374fd53eaacd7d1a7f68e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
This partially reverts commit 32ebaef73c
("mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE")
as google/brox board has moved away from the PAD_CFG_GPI_INT_SWAPPED
usage. The revert simply removes the PAD_CFG_GPI_INT_SWAPPED solution,
which is not used anywhere anymore.
PAD_CFG0_ROUTE_SWAPPED bit can not be found in any PCH datasheet nor
EDS. Furthermore, the definition conflicts with PAD_CFG0_NAFVWE_ENABLE
bit, which, on the contrary, is defined in the datasheets and PCH EDS.
The conflict results in boards printing:
"GPIO XX doesn't support APIC routing," (where XX is pad number)
for each pad having the NAFVWE bit set.
Currently, none of the boards use PAD_CFG0_ROUTE_SWAPPED bit, and due
to the bit field conflict I assume it was mistakenly added.
Change-Id: I71299c9729f294cfafaec02222ef01e96b575740
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87485
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Due to layout restrictions on mc_ehl3, the eMMC interface is limited to
operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not
supported. Limit the capabilities in the eMMC controller to DDR50 mode
only so that the eMMC driver in OS will choose the right mode for
operation even if the attached eMMC card supports higher modes.
BUG=none
TEST=Boot into Linux and check dmesg output for mmc modes
Change-Id: Id84d34e7abd4bf73648d453182345bc2e4676d62
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88110
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Set slow_slew_rate for VCCIA and VCCGT to SLEW_FAST_8 to improve EE
noise for meliks.
BRANCH=nissa
TEST=built firmware and got pass for EE noise test.
Change-Id: Ie1a9147736e3effa465134854ecd34554bee6906
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88126
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Doan <edoan@chromium.org>
This commit eliminates the power limit constraints initially adopted
from the Fatcat board's codebase. These constraints are tailored for
factory-specific scenarios, which are irrelevant to the Intel Panther
Lake RVP (PTLRVP) board's use case.
Change-Id: I3e4dfe85a2677ad3998fd6c0f9a59fa966587c59
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88132
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit addresses an issue within the DMAR (DMA Remapping) table
configuration for Intel Panther Lake (PTL) SoC. Specifically, it
introduces telemetry support to the DRHC structure. In addition, the
unnecessary Dynamic Platform and Thermal Framework (DPTF) entry is
removed from the SATC structure, aligning with the BIOS Requirements.
For detailed specifications, refer to the 812562 PTL Firmware
Architecture Specification (FAS).
BUG=b:423943431
TEST=Boot Fatcat board to ALOS. Disassemble the DMAR table using 2023+
version of iasl and check the DMAR for the telemetry entry in the DRHC
structure. There should not be a DPTF entry in the SATC structure.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I289f2520e4449a6aa33f53040b6c8f66faa4f2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88136
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A need arose to perform power and performance analysis on various SoC
SKUs with Fast VMode enabled, which the current chipset data structure
does not allow.
This commit refactors the configuration of Fast VMode I_TRIP thresholds
for Voltage Regulator (VR) domains across different power limit
configurations in Pantherlake SoCs. Previously, the I_TRIP threshold
values were statically set for each VR domain, but now they are defined
within a two-dimensional array that considers various power limit
scenarios.
This commit adds the I_TRIP values for different Power Limit SKUs
currently operated on Fatcat devices.
As part of this commit, the following two changes are being undone
because the previous code structure is now incompatible and lacks
purpose:
- commit 4b765fdd98 ("mb/google/fatcat: Disable EnableFastVmode on
Panther Lake H SoC")
- commit 5d7e2b4c0c ("mb/google/fatcat: Disable VR settings on Panther
Lake H SoC")
Change-Id: Iff21a9b0b230e08b99e032400cbe0021b8a4af43
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces support for additional Intel Panther Lake CPU IDs
in the `power_optimized_limits` structure, enhancing compatibility with
newer hardware. It also introduces macros for common power limit values,
streamlining the code and reducing repetition.
Change-Id: I6d7c24441ce6ed78c366f18627c237a2f4984cd5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88131
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds the relevant IDs to support new Panther Lake (PTL)
System on Chips (SoCs). The CPU profiles are aligned with the matching
definition from Panther Lake Firmware Support Package (FSP) revision
3144.01.
TEST=A Fatcat device with CPUID 0xc06c1 and MCH_ID 0xb003 booted with
the relevant information printed in corebot logs.
[DEBUG] CPU: ID c06c1, Pantherlake B0, ucode: 00000105
[DEBUG] MCH: device id b003 (rev 06) is Pantherlake U
[DEBUG] PCH: device id e401 (rev 01) is Pantherlake SOC-H SuperSKU
[DEBUG] IGD: device id b090 (rev 00) is Pantherlake-U GT2
Change-Id: I66efe51a94edfffc2546817d06a63a9c4b51aa81
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88130
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit introduces the configuration and enabling of Thermal Design
Current (TDC) settings for various Panther Lake (PTL) SKUs. TDC values
are essential for managing thermal constraints, specifying the maximum
allowable current for specific Voltage Regulator (VR) domains under
given power limit scenarios. This enhancement provides tailored power
management for different SKUs, extracted from the Power Map Document
(#813278) which the Firmware Support Package (FSP) is not aligned with.
It introduces a new enum `soc_intel_pantherlake_sku` to represent
various SKUs as the current `soc_intel_pantherlake_power_limits` does
not meet the need for TDC settings. `cpuid_to_ptl` is updated to include
SKU mapping.
The VR romstage FSP params function implements logic to read SKU
information based on PCI device ID and CPU TDP, ensuring accurate
configuration.
TEST=FSP logs confirm TDC enablement at the specified values on a Fatcat
device operating an H12Xe Panther Lake SoC.
Change-Id: I889d5f08b0c75b950e5a30d25d6a370cccd295aa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88039
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit makes power limit helper functions accessible during
romstage by updating the Makefile to include `power_limit.c` for both
ramstage and romstage.
It also modifies a preprocessor directive to ensure
`variant_update_cpu_power_limits()` is not compiled in romstage as it is
only intended for late-in-the-boot usage and will not compile properly
in romstage.
This change enables power management configuration identification early
in the boot process, allowing for better control over power settings at
this stage.
TEST=Successfully compile the Fatcat board target.
Change-Id: Ibf4d85c71dd8963063ca014d151438b68ea918db
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88038
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit exposes the Thermal Design Current (TDC) limit in the
FSP_M_CONFIG structure. The TDC Current Limit is defined in 1/8A
increments. This allows for more precise control over the thermal design
current settings, enhancing power management capabilities.
Change-Id: Ie35611d5cdc14114542ac1a61611aa333c4bb1c9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
The previous default value of 10 milliseconds is being updated to 50
milliseconds to comply with the latest guidelines (Panther Lake FSP
release 3144.01 CnviWifi.asl file).
TEST=Invoke the following set of acpidbg commands to verify that the
_RST method still reaches state 2.
acpidbg -b 'evaluate \_SB.PCI0.CNVW.PRRS' # 0x0
acpidbg -b 'set N \_SB.PCI0.CNVW.RSTT 1'
acpidbg -b 'evaluate \_SB.PCI0.CNVW.CNVP._RST'
acpidbg -b 'evaluate \_SB.PCI0.CNVW.PRRS' # 0x2
Change-Id: I2b0236c17117d368c1ee98e56c4c1b6525d63e27
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
