Enhance the readability and maintainability of the code by adding
detailed comments for the ACPI names "PRRS" and "RSTT" in the
`cnvw_fill_ssdt` function. These comments clarify the possible status
values for "PRRS" and the reset types for "RSTT", aiding developers in
understanding the function's logic and expected behavior.
Change-Id: I94486476cf2f95b8e1744ee369a9d9d6c734bba8
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88086
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The commit leverages the \_SB.PCI0.BASE() ACPI method to remove the
hardcoded offset in the definition of the ACPI OperationRegion for CNVI
devices. Instead of using a fixed memory address addition, the code now
dynamically calculates the RegionOffset using the device's base address
(_ADR). This change enhances flexibility and adaptability for different
configurations and devices.
TEST=acpidbg -b 'evaluate \_SB.PCI0.CNVW.VDID' returns 0xE4408086 on a
Fatcat device.
Change-Id: Ia329aef0291c31862d002cb9bfa35930dab83fe5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The BASE method, previously located within USB Type-C Subsystem (TCSS)
ASL (ACPI Source Language) scope across multiple Intel System on Chip
(SoC) files, has been moved to the northbridge module. This refactoring
allows the BASE method to be utilized beyond the USB Type-C Subsystem
use-case.
The BASE method calculates the PCIe device base address using function
and device numbers.
Note: the BASE method is now under the \SB.PCI0 scope. It used to be
under the \_SB scope while only consumed by devices under the \SB.PCI0
scope.
TEST=On a Fatcat board, we verified that the BASE method returns
0xE00A3000 for the "./acpidbg -b 'evaluate \_SB.PCI0.BASE
0x140003'" command. We performed a non-regression test as well on
the TCSS DMA TDM0 device, which uses the BASE method, by verifying
that "./acpidbg -b 'evaluate \_SB.PCI0.TDM0.DMAD'" and "./acpidbg
-b 'evaluate \_SB.PCI0.TDM0.VDID'" return 0x22 and 0xE4338086,
respectively.
Change-Id: I431206e9f38a2a5695c90d4ae6d823fb231814aa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
I've found some TODOs in comment in device_util.c,
so I replaced them with descriptions for readability.
Change-Id: I429ce0b2a1b56a60fdb4127591ec219768c2c044
Signed-off-by: NyeonWoo Kim <knw0507@naver.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87907
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors `SPCO` ASL with helpers to remove macros.
1. Avoid inclusion of macros in ASL code.
2. Ensure runtime check can call appropriate clock routine either
for IOE die or PCH/SoC die.
This ensures runtime calls to correct clock routines for IOE,
PCH/SoC. Includes IOE PCR and IOE CLK ASL for compilation.
This inclusion increases the DSDT binary size by 250 bytes.
TEST=Able to build and boot google/fatcat.
w/ this patch:
```
fallback/dsdt.aml 0x94140 raw 25594 none
```
w/o this patch:
```
fallback/dsdt.aml 0x94140 raw 25350 none
```
Change-Id: Iee254e1766ca90662eb04548db26a408ce3c3d88
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87975
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update device tree to support PIXART touchpad.
BUG=b:414734334
TEST=emerge-fatcat coreboot and PIXART touchpad can work well.
Change-Id: I0eaab274e870f45f3cad16805580a968fc4b4aae
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update device tree to support Synaptics touchpad.
BUG=b:414734334
TEST=emerge-fatcat coreboot and Synaptics touchpad can work well.
Change-Id: I5decb88cc37923e80a619899df66d47ec1579914
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88074
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The old wiki no longer exists (see the announcement at [1]), the
current URLs lead to an HTTP 404.
To fix it, replace the URLs with the main page URL, which contains
links to the current documentation, manual, etc.
[1]: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.org/thread/GNT23GQEQ5I5JCJ6YKUSRXD7JORSG4RV/
Change-Id: Ifb430a033d12f8064893f75315d577b5e78ffc9e
Signed-off-by: Raphaël Mélotte <raphael.melotte@mind.be>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Ocelotmchp is the same as the ocelot variant except that it uses the
Microchip EC.
BUG=b:419857124
BRANCH=none
TEST=`emerge-ocelot coreboot` and verify it builds without error.
Change-Id: I9088a57289d9ef489a7773a8d828d5f945440757
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88060
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ocelotite is the same as the ocelot veriant except that it uses the
ITE EC.
BUG=b:419856369
BRANCH=None
TEST=`emerge-ocelot coreboot` and verify it builds without error.
Change-Id: I1871d5772ea1a73d55d49bdac5b00a17f524eeeb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88059
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace RSMRST with PLTRST, for the PCH Strap GPIOs. RSMRST introduced
programming errors in cbmem (gpio_pad_reset_config_override: logical
to chipset mapping not found) and broke tablet mode rotation.
Change-Id: Ia2b655450558a9de98ce1a92c93820ab3da57ca0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88053
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This case doesn't reflect an error condition, so adjust the printk
level accordingly.
Change-Id: I3afa818447d3e7c9d08968ffc6b57a663af45c3e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88011
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The generic device attached to this driver doesn't have resources
separate from the parent device to which it's attached, so
use 'noop_read_resources' to suppress a false-positive error in
the cbmem console log (GENERIC: 0.0 missing read_resources).
Change-Id: I985318dcc7cc32aaa3f6a599ade95e065900031e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88012
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ME region is 0x1000 smaller for Twin Lake, so adjust it
accordingly.
Change-Id: I8d4a279597b31f05c6181218c4a07acdfc676920
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Rather than always enabling TME_KEY_REGENERATION_ON_WARM_BOOT, allow it
to be deselected but default to Y. Enabling it causes issues on boards
which use S3 suspend (vs S0ix), so allow it to be deselected so those
boards don't have to disable TME entirely.
TEST=build/boot starlabs/starbook_mtl, verify S3 resume works properly
with TME_KEY_REGENERATION_ON_WARM_BOOT deselected.
Change-Id: I60de19eddf7c2d8bc390b718b7cb1bf7d0267d47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88054
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Provide a valid GPIO configuration based on the mainboard wiring.
BUG=none
TEST=Checked output of verbose GPIO debug messages.
Change-Id: I75570acf2bb11a99b99fe70b9d639837daee125c
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87913
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On the Fatcat board, the following ACPI error message was observed.
After applying the modification, the issue no longer appears.
ACPI error message via dmesg:
[ 0.209800] ACPI: Enabled 2 GPEs in block 00 to 7F
[ 0.210654] ACPI: \: Can't tag data node
[ 0.211039] ACPI: \: Can't tag data node
[ 0.211430] ACPI: \: Can't tag data node
[ 0.211672] ACPI: \: Can't tag data node
[ 0.212052] ACPI: \: Can't tag data node
BUG:None
TEST:Run 'dmesg | grep -i "Can't tag data node" -A 10 -B 10' and cannot see the error messages anymore.
Change-Id: I3da251b3c1950611fa0b4c125823f89d91dcd804
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Key changes:
- Updated ACPI southbridge configuration to include UFS support
for Wildcat Lake.
- Modified FSP parameters to enable UFS controllers for
Wildcat Lake.
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.
Change-Id: I3878b4a54a7be2565b37b0f885af5d55a6778795
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
DRAM Part Name ID to assign
H58G56CK8BX146 7 (0111)
BUG=b:424334614
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I35aa833372eced9b7906b4c46b9e3389fcb364f5
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88067
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DRAM Part Name ID to assign
H58G56CK8BX146 7 (0111)
BUG=b:424334614
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I9ca77d07908502649f3bc5380071ca1edceba997
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88066
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SPI_BASE_ADDRESS is a fixed value to align with SoC and FSP usage.
Use Kconfig to define it so that SoC could override it per their needs.
Change-Id: If5e5338106deb18d108a70f5ffcd96dcb1e5e25a
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
fast_spi_cache_bios_region() refers to the SPI BAR before it is
initialized. Therefore, move the initialization before this function
to obtain the correct value.
If SPI is not initialized before use, an incorrect MTRR item is observed:
[DEBUG] 0x00000000fffff005: PHYBASE2: Address = 0x00000000fffff000, WP
[DEBUG] 0x000ffffffffff800: PHYMASK2: Length = 0x0000000000001000, Valid
TESTED=Build and boot on intel/avenuecity CRB, with below log:
[DEBUG] 0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP
[DEBUG] 0x000fffffff000800: PHYMASK2: Length = 0x0000000001000000, Valid
Change-Id: I8a755d2d18a567c09c5a66b03d4fdda5ba603133
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88046
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
We use mmu_ranges to track the list of memory ranges and their types for
MMU initialization. We also keep track of used memory ranges in
usedmem_ranges, to avoid them from being re-allocated in
mmu_alloc_range().
The problem is, the CBMEM range (CB_MEM_TABLE) is added to mmu_ranges,
but is never marked as "used" in usedmem_ranges. This potentially causes
any allocation (for example the framebuffer) to overlap with CBMEM. This
issue is observed when DMA_DEFAULT_SIZE is reduced from 32MB to 1MB [1].
Prior to that change, because there isn't enough space above the
coreboot table (with the 4GB upper limit) to fit the 32MB requested
region, the DMA heap is always allocated *below* the coreboot table. And
because the coreboot table is usually the lowest within CBMEM, the DMA
heap region is allocated *below* the whole CBMEM, which happens the
avoid the issue.
Fix the bug by adding CB_MEM_TABLE ranges to usedmem_ranges. The ranges
in usedmem_ranges don't need to be combined because they are not for MMU
initialization (and there's only one CB_MEM_TABLE range).
[1] commit aedc177f00 ("libpayload: arm64: Reduce DMA allocator space to 1MB")
BUG=b:424107889
TEST=emerge-skywalker libpayload
BRANCH=none
Change-Id: Ie9ecafc17546e524253c60ab684ec10ff3495998
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
This adds the release notes template for the upcoming September release
of coreboot.
Change-Id: I9033b107f148b4b40bb1243d2d0eb0b7e7f7b6dc
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Alter dram from H9JCNNNCP3MLYR-N6E to H9JCNNNBK3MLYR-N6E
BUG=b:395763555
BRANCH=none
TEST=Could boot to OS.
Change-Id: Id2b024286b3699015be3a25341389db353d1ab8f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88061
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The console UART base address for Panther Lake is being updated from
0xfe02c000 to 0xfe036000 (as per FSP version 3182). This correction
ensures the console initializes with the correct UART base address.
Additionally, now the UART base address is in sync between coreboot,
FSP and GFX PEIM.
BUG=b:423878608
TEST=Able to get FSP debug log while building google/fatcat.
```
dw-apb-uart.3: ttyS0 at MMIO 0xfe036000
```
Change-Id: I0caae8b5ea34561d88f5a4aa0cb12481db6f9417
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88073
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update header files for FSP for Panther Lake platform to version
3182.01, previous version being 3144.01.
Changes include:
- Update FspmUpd.h
- Add PprRetryLimit and Use1p5ReadPostamble variable
BUG=b:421287370
TEST=Able to build google/fatcat with the partial header changes
Change-Id: I14e8c3c8751ae6aa0718d0015a1611ced6a2cdd4
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87879
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
GPP_D07 was modified in CB:87806, which resulted in the dut having no camera function. Now we need to restore the configuration of GPP_D07.
BUG=NONE
TEST=emerge-fatcat coreboot and find that the camera function is good.
CB:87806: mb/google/fatcat/var/felino: Modify GPIOs config: I075efda3044ffe45d7db3d225b10e96e084483aa
Change-Id: I085c98753614a0b72f191a863b68990775832c98
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88025
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Create an ocelot model for the various ocelot variants to use.
BUG=b:419857124, b:419856369
BRANCH=none
TEST=`emerge-ocelot coreboot` and verify it compiles without error.
Change-Id: I61e636beb74c3b1ef36e1b9737aefe0b0ef104c5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Add NANYA NT6AP512T32BL-J1 as id 2, and add NANYA NT6AP1024T32BL-J1
as id 3, resulting in the list below:
DRAM Part Name ID to assign
K4U6E3S4AB-MGCL 0 (0000)
K4UBE3D4AB-MGCL 1 (0001)
MT53E1G32D2NP-046 WT:B 1 (0001)
NT6AP512T32BL-J1 2 (0010)
NT6AP1024F32BL-J1 3 (0011)
BUG=422906387
TEST=Use part_id_gen to generate related settings
Change-Id: Ifd60e629eb606c7ce06f478cf7cc8b8b3ec77f74
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88005
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Since CB:84118 / 3d5ff65b27 (mb/google/cherry: Complete PCIe reset in
romstage) google-cherry mainboards do an early PERST# de-assert in
romstage. Since cherry does not have a pci_domain, `pci_root_bus()` will
return null, causing an assertion failure later in `find_dev_path()`.
Return if `pci_root_bus()` is NULL.
TEST=Successful boot on google/tomato
Change-Id: Icc35a53e38eef0088371592d8216ac74f9542166
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Update override devicetree based on schematic_1433518.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I88a3729ff2a61a383a4715a335062310cba01f24
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This reverts commit aedc177f00.
Reason for revert: With this change depthchange clears parts of cbmem on Google/Corsola when display is cleared.
BUG=b:424107889
Change-Id: I6cc21693ddcaed59e41e333b773e0baeb29d3b40
Signed-off-by: Bartłomiej Grzesik <bgrzesik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88051
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add the default configuration for fans as seen in the OS with
superiotool.
Change-Id: Iba142c2ad683962ee2c007f387e87adc77352dad
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add early EC space configuration as done in the vendor BIOS.
Change-Id: I058560733e3f5bb8c6df7d5401efad87911d3f4a
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Based on similar NCT6687D chip. Obtained the NCT6686D EC Space
Specification datasheet from Nuvoton via email request. Most of
the register definitions come from the EC Space Specification,
the rest has been figured out from MSI MS-7D25 BIOS.
Change-Id: I162f9d4067f0cba1d22d6cb5f98b68987719c038
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
The R520G6SB server represents the next generation of the M50FCP2UR
Intel Server System, delivering cutting-edge performance and
versatility tailored for demanding data center and enterprise
workloads. Designed as a 2U dual-socket (2S) Birch Stream SP server
system, it integrates advanced features to meet demanding computing,
networking, and AI-driven application requirements.
Tested:
- USB: Front Panel 2 USB ports and 1 USB port on DCSCM
- PCIe: J1_MXIO_SLOT1 ~ J1_MXIO_SLOT5 (with PCIe SATA controller)
- M.2: M2_CN1, M2_CN2
- Mini Display Port
- Flash firmware from BMC's redfish interface (Out-of-band)
Build with Linux payload and Intel proprietary FSP.
Installed with dual Intel® Xeon® 6756E, one Micron 64GB DDR5
RDIMM 4800 and boots to Ubuntu 22.04.5 LTS (6.8.0-57-generic).
Change-Id: I0590c82c9763bd07348bd86b134007ea4ed71d7a
Signed-off-by: Schumi Chu <schumi.chu@mitaccomputing.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87574
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SC513G6 is a high-performance single-socket server motherboard
designed for AI, HPC, cloud, and data center applications.
Featuring Intel® Xeon® 6 Processors(LGA4710) support with up to
350W TDP, it delivers exceptional compute power, high-speed
networking, and versatile storage options in a compact SSI CEB
form factor.
Tested:
- USB: 4 USB ports
- PCIe: PCIE#1, PCIE#2, PCIE#3, PCIE#5 (with PCIe SATA controller,
and PCIE#4 is only available on CPU R1S SKU)
- M.2: M.2#1 and M.2#2
- LAN: 2 RJ45 GbE ports
- Graphic VGA Port
- - Flash firmware from BMC's redfish interface (Out-of-band)
Installed with Intel® Xeon® 6756E and boots to
Ubuntu 22.04.5 LTS (6.8.0-57-generic).
Change-Id: I7b85e8548cfbdf9e52dc1956bd33e829020c052c
Signed-off-by: Schumi Chu <schumi.chu@mitaccomputing.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add some simple execution time measurement code. It only logs execution
times if `DEBUG_RAM_SETUP` is selected. Note that this will fill things
like pre-RAM CBMEM console, but NRI's debug output is already extremely
verbose, and will become even more verbose as additional training steps
get added.
Future plans include measuring the time spent waiting for REUT hardware
to finish testing, as that is what takes most time for complex training
algorithms (which are yet to be published).
Tested on Asrock B85M Pro4, still boots to Arch Linux. Output example:
+------------------+------------+
| Task | msecs |
+------------------+------------+
| PROCSPD | 503 |
| INITMPLL | 33 |
| CONVTIM | 43 |
| CONFMC | 1 |
| MEMMAP | 39 |
| JEDECINIT | 1 |
| PRETRAIN | 23 |
| SOT | 394 |
| RCVET | 1448 |
| RDMPRT | 1088 |
| JWRL | 1975 |
| OPTCOMP | 0 |
| POSTTRAIN | 0 |
| ACTIVATE | 0 |
| SAVE_TRAIN | 0 |
| SAVE_NONT | 0 |
| RAMINITEND | 4 |
+------------------+------------+
| Total | 5558 |
+------------------+------------+
Note: the board had 4x dual-rank DIMMs installed, which gives the worst
possible boot time (more ranks to train, and that means more log output
to push through 115200 baud serial). Without debug logging, training is
substantially faster.
Change-Id: Ie4b6f6246e54f23d03babdb6fa0271538f69984e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87830
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update TPM related default values for DRIVER_TPM_I2C_BUS and
TPM_TIS_ACPI_INTERRUPT based on schematic_1433518.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: Ifbd99265a36602b7d820cc088317579496144c9d
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I29070d871666f42615ba7afae9b9adb07e089fdc
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392 b:421064225
TEST=Run suspend_stress_test on moxie and verify that the device
suspends to S0ix.
Change-Id: I6b2c264fd7244ab84e82919354afb2b49a22177a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88000
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
FMAP_SECTION_SI_BIOS_START is used to pass host address for UPD
BiosRegionBase. It changes to flash address after:
commit 2efe4df522 ("treewide: Assume FMAP_SECTION_FLASH_START = 0")
Convert FMAP_SECTION_SI_BIOS_START to host address to set
BiosRegionBase.
TESTED=Build and boot on intel/beechnutcity CRB, check boot log with:
[INFO ] BiosRegionBase is set to ff000000
[INFO ] BiosRegionSize is set to 1000000
Change-Id: Ie115bd8e9044455185f82885a306849c509157bb
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87690
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FMAP_SECTION_SI_BIOS_START is used to pass host address for UPD
BiosRegionBase. It changes to flash address after:
commit 2efe4df522 ("treewide: Assume FMAP_SECTION_FLASH_START = 0")
Convert FMAP_SECTION_SI_BIOS_START to host address to set
BiosRegionBase.
TESTED=Build and boot on intel/avenuecity CRB, check boot log with:
[INFO ] BiosRegionBase is set to ff000000
[INFO ] BiosRegionSize is set to 1000000
Change-Id: I92589253915ad88bbb73736e10e7524b6be82499
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87689
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a mapping for the Core 3 N350 SoC, which has a MCH with PCI DID
0x4617, 8 efficiency cores, and a 7W TDP. This eliminates an error when
setting power limits due to the missing entry:
[ERROR] unknown SA ID: 0x4617, skipped power limits configuration
TEST=build/boot starlabs/starlite_adl with ADL-N Core 3 N350 SoC.
Change-Id: Ibd701ec5589a9a023a5538f470ff234a23249b45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
