erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/lenovo/m900/devicetree.cb: Use OC6 enum

Browse source 
Commit 0e5d1d29bd ("soc/intel/skylake: Expand USB OC pins enum to
OC7") added the missing OC6 and OC7 enums for PCH-H, so use those
instead of a bare integer to map USB2 ports 10 and 11 to overcurrent
pin 6.

TEST=Timeless build did not change

Change-Id: I3680fae39e96783e4434b36a8dfd751888541cbb
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Nicholas Chin 2025-06-21 09:05:43 -06:00 • committed by Matt DeVillier
commit a66d2d41f5
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/mainboard/lenovo/m900/devicetree.cb
View file

@ -54,8 +54,8 @@ chip soc/intel/skylake
[7] = USB2_PORT_MID(OC3), /* Rear port 4 */
[8] = USB2_PORT_MID(OC5), /* FUSB_1 Header */
[9] = USB2_PORT_MID(OC5), /* FUSB_1 Header */
[10] = USB2_PORT_MID(6), /* FUSB_2 Header */
[11] = USB2_PORT_MID(6), /* FUSB_2 Header */
[10] = USB2_PORT_MID(OC6), /* FUSB_2 Header */
[11] = USB2_PORT_MID(OC6), /* FUSB_2 Header */
[12] = USB2_PORT_MID(OC1), /* Rear port 7 */
[13] = USB2_PORT_MID(OC1), /* Rear port 8 */
}"