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mb/trulo/var/kaladin: Create kaladin variant

Browse source 
Create the kaladin variant of trulo reference board by copying the
template files to a new directory named for the variant.

Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.

BUG=b:420836320
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KALADIN

Change-Id: Ib0cbe8c4c0d988aec1bab0f272d1abd532cbc54f
Signed-off-by: wu.garen <wu.garen@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
wu.garen 2025-06-09 23:28:58 +08:00 • committed by Matt DeVillier
commit 1f28803dcd
12 changed files with 1259 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

12
src/mainboard/google/brya/Kconfig
View file

@ -321,6 +321,14 @@ config BOARD_GOOGLE_HADES
select RT8168_GET_MAC_FROM_VPD
select RT8168_SET_LED_MODE
config BOARD_GOOGLE_KALADIN
select BOARD_GOOGLE_BASEBOARD_TRULO
select CHROMEOS_WIFI_SAR if CHROMEOS
select DRIVERS_GENERIC_GPIO_KEYS
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
select SOC_INTEL_TWINLAKE
config BOARD_GOOGLE_KANO
select BOARD_GOOGLE_BASEBOARD_BRYA
select CHROMEOS_WIFI_SAR if CHROMEOS
@ -841,6 +849,7 @@ config DRIVER_TPM_I2C_BUS
default 0x3 if BOARD_GOOGLE_HADES
default 0x0 if BOARD_GOOGLE_JOXER
default 0x1 if BOARD_GOOGLE_KANO
default 0x0 if BOARD_GOOGLE_KALADIN
default 0x1 if BOARD_GOOGLE_KINOX
default 0x1 if BOARD_GOOGLE_KULDAX
default 0x1 if BOARD_GOOGLE_LISBON
@ -928,6 +937,7 @@ config TPM_TIS_ACPI_INTERRUPT
default 20 if BOARD_GOOGLE_HADES # GPE0_DW0_20 (GPP_A20_IRQ)
default 13 if BOARD_GOOGLE_JOXER
default 13 if BOARD_GOOGLE_KANO
default 13 if BOARD_GOOGLE_KALADIN
default 13 if BOARD_GOOGLE_KINOX
default 13 if BOARD_GOOGLE_KULDAX
default 13 if BOARD_GOOGLE_LISBON
@ -1019,6 +1029,7 @@ config MAINBOARD_PART_NUMBER
default "Hades" if BOARD_GOOGLE_HADES
default "Joxer" if BOARD_GOOGLE_JOXER
default "Kano" if BOARD_GOOGLE_KANO
default "Kaladin" if BOARD_GOOGLE_KALADIN
default "Kinox" if BOARD_GOOGLE_KINOX
default "Kuldax" if BOARD_GOOGLE_KULDAX
default "Lisbon" if BOARD_GOOGLE_LISBON
@ -1099,6 +1110,7 @@ config VARIANT_DIR
default "hades" if BOARD_GOOGLE_HADES
default "joxer" if BOARD_GOOGLE_JOXER
default "kano" if BOARD_GOOGLE_KANO
default "kaladin" if BOARD_GOOGLE_KALADIN
default "kinox" if BOARD_GOOGLE_KINOX
default "kuldax" if BOARD_GOOGLE_KULDAX
default "lisbon" if BOARD_GOOGLE_LISBON

3
src/mainboard/google/brya/Kconfig.name
View file

@ -77,6 +77,9 @@ config BOARD_GOOGLE_HADES
config BOARD_GOOGLE_KANO
bool "-> Kano"
config BOARD_GOOGLE_KALADIN
bool "-> Kaladin"
config BOARD_GOOGLE_KINOX
bool "-> Kinox"

7
src/mainboard/google/brya/variants/kaladin/Makefile.mk Normal file
View file

@ -0,0 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
romstage-y += memory.c
ramstage-y += gpio.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c

487
src/mainboard/google/brya/variants/kaladin/gpio.c Normal file
View file

@ -0,0 +1,487 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <variant/gpio.h>
#include <baseboard/variants.h>
#include <soc/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
/* Pad configuration in ramstage */
static const struct pad_config gpio_table[] = {
/* A0 thru A4, A9 and A10 come configured out of reset, do not touch */
/* A0 : ESPI_IO0 ==> ESPI_SOC_D0_EC */
/* A1 : ESPI_IO1 ==> ESPI_SOC_D1_EC */
/* A2 : ESPI_IO2 ==> ESPI_SOC_D2_EC */
/* A3 : ESPI_IO3 ==> ESPI_SOC_D3_EC */
/* A4 : ESPI_CS0# ==> ESPI_SOC_CS_EC_L */
/* A5 : ESPI_ALERT0# ==> NC */
PAD_NC(GPP_A5, NONE),
/* A6 : ESPI_ALERT1# ==> NC */
PAD_NC(GPP_A6, NONE),
/* A7 : NC */
PAD_NC(GPP_A7, NONE),
/* A8 : GPP_A8 ==> NC */
PAD_NC(GPP_A8, NONE),
/* A9 : ESPI_CLK ==> ESPI_SOC_CLK */
/* A10 : ESPI_RESET# ==> ESPI_SOC_RST_EC_L */
/* A11 : SSD_PERST_L */
PAD_CFG_GPO(GPP_A11, 1, DEEP),
/* A12 : NC */
PAD_NC(GPP_A12, NONE),
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* A14 : USB_A0_FAULT_ODL */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* A15 : NC */
PAD_NC(GPP_A15, NONE),
/* A16 : USB_OC3# */
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
/* A17 : NC */
PAD_NC(GPP_A17, NONE),
/* A18 : NC */
PAD_NC(GPP_A18, NONE),
/* A19 : NC */
PAD_NC(GPP_A19, NONE),
/* A20 : NC */
PAD_NC(GPP_A20, NONE),
/* A21 : USB_C1_AUX_DC_P */
PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
/* A22 : USB_C1_AUX_DC_N */
PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
/* A23 : GPP_A23 ==> NC */
PAD_NC(GPP_A23, NONE),
/* B0 : VCCIN_AUX_VID0 */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
/* B1 : VCCIN_AUX_VID1 */
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
/* B2 : NC */
PAD_NC(GPP_B2, NONE),
/* B3 : IMU_INT_L */
PAD_CFG_GPI_APIC(GPP_B3, NONE, PWROK, LEVEL, INVERT),
/* B4 : ACC_INT_L */
PAD_CFG_GPI_APIC(GPP_B4, NONE, PWROK, LEVEL, INVERT),
/* B5 : GPP_B5 ==> ISH_I2C0_SENSOR_SDA */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B5, NONE, DEEP, NF1),
/* B6 : GPP_B6 ==> ISH_I2C0_SENSOR_SCL */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B6, NONE, DEEP, NF1),
/* B7 : I2C3_SDA ==> NC */
PAD_NC(GPP_B7, NONE),
/* B8 : I2C3_SCL ==> NC */
PAD_NC(GPP_B8, NONE),
/* B9 : Not available */
PAD_NC(GPP_B9, NONE),
/* B10 : Not available */
PAD_NC(GPP_B10, NONE),
/* B11 : SOC_PD0_INT# */
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
/* B12 : SLP_S0# ==> PM_SLP_S0# */
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* B13 : PLTRST# ==> PLT_RST_L */
PAD_CFG_NF_LOCK(GPP_B13, NONE, NF1, LOCK_CONFIG),
/* B14 : GPP_B14_STRAP */
PAD_NC(GPP_B14, NONE),
/* B15 : NC */
PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
/* B16 : GPP_B16 ==> I2C_TOUCHPAD_SDA */
PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
/* B17 : GPP_B17 ==> I2C_TOUCHPAD_SCL */
PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
/* B18 : GPP_B18 ==> GPP_B18_STRAP */
PAD_NC(GPP_B18, NONE),
/* B19 : Not available */
PAD_NC(GPP_B19, NONE),
/* B20 : Not available */
PAD_NC(GPP_B20, NONE),
/* B21 : Not available */
PAD_NC(GPP_B21, NONE),
/* B22 : Not available */
PAD_NC(GPP_B22, NONE),
/* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
PAD_NC(GPP_B23, NONE),
/* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */
PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C1 : SMBDATA ==> TCHSCR_RST_L */
PAD_CFG_GPO(GPP_C1, 1, DEEP),
/* C2 : SMBALERT# ==> GPP_C2_STRAP */
PAD_NC(GPP_C2, NONE),
/* C3 : EN_PP3300_UCAM_X */
PAD_CFG_GPO_LOCK(GPP_C3, 1, LOCK_CONFIG),
/* C4 : TCHSCR_REPORT_EN */
PAD_CFG_GPO(GPP_C4, 0, DEEP),
/* C5 : SML0ALERT# ==> GPP_C5_STRAP */
PAD_NC(GPP_C5, NONE),
/* C6 : I2C_SOC_PMC_PD_SCL */
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
/* C7 : I2C_SOC_PMC_PD_SDA */
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
/* D0 : SEN_MODE2_EC_PCH_INT_ODL */
PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
/* D1 : ISH_GP1 ==> SEN_MODE2_EC_ISH_INT_ODL */
PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
/* D2 : NC */
PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
/* D3 : ISH_GP3 ==> NC */
PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
/* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */
PAD_CFG_GPO(GPP_D4, 1, DEEP),
/* D5 : SSD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
/* D6 : SRCCLKREQ1# ==> NC */
PAD_NC_LOCK(GPP_D6, NONE, LOCK_CONFIG),
/* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
/* D8 : SRCCLKREQ3# ==> NC */
PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
/* D9 : NC */
PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
/* D11 : NC */
PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
/* D13 : UART0_ISH_RX_DBG_TX */
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
/* D14 : UART0_ISH_TX_DBG_RX */
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* D15 : ISH_UART0_RTS# ==> NC */
PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
/* D16 : ISH_UART0_CTS# ==> NC */
PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
/* D17 : NC */
PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
/* D18 : NC */
PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
/* D19 : I2S_MCLK1_OUT ==> CPUID */
PAD_CFG_GPI(GPP_D19, NONE, DEEP),
/* E0 : NC */
PAD_NC_LOCK(GPP_E0, NONE, LOCK_CONFIG),
/* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_0 */
PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
/* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
/* E3 : PROC_GP0 ==> MEM_STRAP_2 */
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
/* E4 : NC */
PAD_NC(GPP_E4, NONE),
/* E5 : NC */
PAD_NC(GPP_E5, NONE),
/* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */
PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
/* E7 : NC */
PAD_NC(GPP_E7, NONE),
/* E8 : GPP_E8 ==> WLAN_DISABLE_L */
PAD_CFG_GPO(GPP_E8, 1, DEEP),
/* E9 : SOC_USB_OC0 */
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* E10 : EN_PP3300_WLAN_X */
PAD_CFG_GPO(GPP_E10, 1, DEEP),
/* E11 : TCHSCR_INT_ODL */
PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT),
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG),
/* E13 : THC0_SPI1_IO0 ==> NC*/
PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
/* E14 : DDSP_HPDA ==> EDP_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* E15 : NC */
PAD_NC(GPP_E15, NONE),
/* E16 : NC */
PAD_NC(GPP_E16, NONE),
/* E17 : MEM_STRAP_3 */
PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG),
/* E18 : NC */
PAD_NC(GPP_E18, NONE),
/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
PAD_NC(GPP_E19, NONE),
/* E20 : DDP2_CTRLCLK ==> NC */
PAD_NC(GPP_E20, NONE),
/* E21 : DDP2_CTRLDATA ==> NC */
PAD_NC(GPP_E21, NONE),
/* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */
PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
/* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */
PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
/* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
/* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
/* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
/* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
/* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
/* F5 : CRF_XTAL_CLKREQ ==> CNV_CLKREQ0 */
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),
/* F6 : CNV_PA_BLANKING ==> NC */
PAD_NC(GPP_F6, NONE),
/* F7 : GPP_F7 ==> GPP_F7_STRAP */
PAD_NC(GPP_F7, NONE),
/* F8 : Not available */
PAD_NC(GPP_F8, NONE),
/* F9 : Not available */
PAD_NC(GPP_F9, NONE),
/* F10 : GPP_F10 ==> GPP_F10_STRAP */
PAD_NC(GPP_F10, NONE),
/* F11 : NC */
PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
/* F12 : NC */
PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
/* F13 : NC */
PAD_NC(GPP_F13, NONE),
/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT),
/* F15 : NC */
PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
/* F16 : NC */
PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG),
/* F18 : THC1_SPI2_INT# ==> NC */
PAD_NC(GPP_F18, NONE),
/* F19 : Not available */
PAD_NC(GPP_F19, NONE),
/* F20 : Not available */
PAD_NC(GPP_F20, NONE),
/* F21 : Not available */
PAD_NC(GPP_F21, NONE),
/* F22 : NC */
PAD_NC(GPP_F22, NONE),
/* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
/* H0 : GPP_H0_STRAP */
PAD_NC(GPP_H0, NONE),
/* H1 : GPP_H1_STRAP */
PAD_NC(GPP_H1, NONE),
/* H2 : GPP_H2_STRAP */
PAD_NC(GPP_H2, NONE),
/* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
/* H6 : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
/* H7 : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
/* H8 : NC */
PAD_NC(GPP_H8, NONE),
/* H9 : NC */
PAD_NC(GPP_H9, NONE),
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* H12 : GPP_H12 ==> NC */
PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
/* H13 : GPP_H13 ==> NC */
PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
/* H14 : Not available */
PAD_NC(GPP_H14, NONE),
/* H15 : DDPB_CTRLCLK ==> NC */
PAD_NC_LOCK(GPP_H15, NONE, LOCK_CONFIG),
/* H16 : Not available */
PAD_NC(GPP_H16, NONE),
/* H17 : DDPB_CTRLDATA ==> PD_SOC_DBG_L */
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
/* H18 : PROC_C10_GATE# ==> CPU_C10_GATE# */
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
/* H19 : SOC_I2C_SUB_INT_ODL */
PAD_NC(GPP_H19, NONE),
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
PAD_CFG_GPO(GPP_H20, 1, DEEP),
/* H21 : NC */
PAD_NC(GPP_H21, NONE),
/* H22 : IMGCLKOUT3 ==> NC */
PAD_NC(GPP_H22, NONE),
/* H23 : GPP_H23 ==> X360_CS_SKU_ID */
PAD_CFG_GPI(GPP_H23, NONE, DEEP),
/* R0 : HDA_BCLK ==> HDA_HP_BCLK */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
/* R1 : HDA_SYNC ==> HDA_HP_SYNC */
PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1),
/* R2 : HDA_SDO ==> HDA_HP_SDO */
PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1),
/* R3 : HDA_SDI0 ==> HDA_HP_SDIN0_R */
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1),
/* R4 : HDA_RST# ==> DMIC_UCAM_CLK */
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
/* R5 : HDA_SDI1 ==> DMIC_UCAM_DATA */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
/* R6 : DMIC_CLK_A_1A ==> NC */
PAD_NC(GPP_R6, NONE),
/* R7 : DMIC_DATA_1A ==> NC */
PAD_NC(GPP_R7, NONE),
/* S0 : I2S_SPK_BCLK_R ==> NC */
PAD_NC(GPP_S0, NONE),
/* S1 : I2S_SPK_LRCK_R ==> NC */
PAD_NC(GPP_S1, NONE),
/* S2 : DMIC_CKL_A0 ==> NC */
PAD_NC(GPP_S2, NONE),
/* S3 : DMIC_DATA0 ==> NC */
PAD_NC(GPP_S3, NONE),
/* S4 : NC */
PAD_NC(GPP_S4, NONE),
/* S5 : NC */
PAD_NC(GPP_S5, NONE),
/* S6 : NC */
PAD_NC(GPP_S6, NONE),
/* S7 : NC */
PAD_NC(GPP_S7, NONE),
/* I5 : NC */
PAD_NC(GPP_I5, NONE),
/* I7 : EMMC_CMD */
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
/* I8 : EMMC_DATA0 */
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
/* I9 : EMMC_DATA1 */
PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
/* I10 : EMMC_DATA2 */
PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
/* I11 : EMMC_DATA3 */
PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
/* I12 : EMMC_DATA4 */
PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
/* I13 : EMMC_DATA5 */
PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
/* I14 : EMMC_DATA6 */
PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
/* I15 : EMMC_DATA7 */
PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
/* I16 : EMMC_RCLK */
PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
/* I17 : EMMC_CLK */
PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
/* I18 : EMMC_RESET# */
PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
/* GPD0 : BATLOW# ==> SOC_BATLOW_L */
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
/* GPD1 : ACPRESENT ==> SOC_ACPRESENT */
PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
/* GPD2 : EC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPD2, NONE, PLTRST, LEVEL, INVERT),
/* GPD3 : PWRBTN# ==> EC_SOC_PWR_BTN_ODL */
PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
/* GPD4 : SLP_S3# ==> SLP_S3_L */
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
/* GPD5 : SLP_S4# ==> SLP_S4_L */
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
/* GPD6 : SLP_A# ==> NC */
PAD_NC(GPD6, NONE),
/* GPD7 : GPD7_STRAP */
PAD_NC(GPD7, NONE),
/* GPD8 : SUSCLK ==> PCH_SUSCLK */
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
/* GPD9 : NC */
PAD_NC(GPD9, NONE),
/* GPD10 : SLP_S5# ==> NC */
PAD_NC(GPD10, NONE),
/* GPD11 : NC */
PAD_NC(GPD11, NONE),
/* Configure the unused virtual CNVi Bluetooth UART pads to NC mode. */
/* vCNV_BT_UART_TXD */
PAD_NC(GPP_VGPIO_6, NONE),
/* vCNV_BT_UART_RXD */
PAD_NC(GPP_VGPIO_7, NONE),
/* vCNV_BT_UART_CTS_B */
PAD_NC(GPP_VGPIO_8, NONE),
/* vCNV_BT_UART_RTS_B */
PAD_NC(GPP_VGPIO_9, NONE),
/* Configure the unused vUART for Bluetooth pads to NC mode. */
/* vUART0_TXD */
PAD_NC(GPP_VGPIO_18, NONE),
/* vUART0_RXD */
PAD_NC(GPP_VGPIO_19, NONE),
/* vUART0_CTS_B */
PAD_NC(GPP_VGPIO_20, NONE),
/* vUART0_RTS_B */
PAD_NC(GPP_VGPIO_21, NONE),
/* Configure the virtual CNVi Bluetooth I2S GPIO Pads.*/
/* BT_I2S_BCLK */
PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
/* BT_I2S_SYNC */
PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
/* BT_I2S_SDO */
PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
/* BT_I2S_SDI */
PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
/* SSP2_SCLK */
PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
/* SSP2_SFRM */
PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
/* SSP_TXD */
PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
/* SSP_RXD */
PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* C0 : SMBCLK ==> EN_PP3300_TCHSCR_X */
PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C1 : SMBDATA ==> TCHSCR_RST_L */
PAD_CFG_GPO(GPP_C1, 1, DEEP),
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
PAD_CFG_GPO(GPP_H20, 0, DEEP),
};
/* Fill romstage gpio configuration */
static const struct pad_config romstage_gpio_table[] = {
};
const struct pad_config *variant_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
return gpio_table;
}
const struct pad_config *variant_gpio_override_table(size_t *num)
{
*num = 0;
return NULL;
}
const struct pad_config *variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
};
DECLARE_CROS_GPIOS(cros_gpios);
const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(romstage_gpio_table);
return romstage_gpio_table;
}

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src/mainboard/google/brya/variants/kaladin/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0236, // Codec Vendor / Device ID: Realtek ALC236
0x103C8C60, // Subsystem ID
0x00000017, // Number of jacks (NID entries)
AZALIA_RESET(0x1),
/* NID 0x01, HDA Codec Subsystem ID Verb table */
AZALIA_SUBVENDOR(0, 0x103C8C60),
/* Pin Widget Verb Table */
/*
* DMIC
* Requirement is to use PCH DMIC. Hence,
* commented out codec's Internal DMIC.
* AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
* AZALIA_PIN_CFG(0, 0x13, 0x40000000),
*/
/* Pin widget 0x14 - Front (Port-D) */
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
/* Pin widget 0x18 - NPC */
AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
/* Pin widget 0x19 - MIC2 (Port-F) */
AZALIA_PIN_CFG(0, 0x19, 0x03A11020),
/* Pin widget 0x1A - LINE1 (Port-C) */
AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
/* Pin widget 0x1B - NPC */
AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
/* Pin widget 0x1D - BEEP-IN */
AZALIA_PIN_CFG(0, 0x1d, 0x40600001),
/* Pin widget 0x1E - NPC */
AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
/* Pin widget 0x21 - HP1-OUT (Port-I) */
AZALIA_PIN_CFG(0, 0x21, 0x03211040),
/*
* Widget node 0x20 - 1
*/
0x0205003C,
0x02040354,
0x0205003C,
0x02040314,
/*
* Widget node 0x20 - 2
* Set JD2 pull high
*/
0x0205001B,
0x02040A4B,
0x0205000B,
0x02047778,
/*
* Widget node 0x20 - 3
*/
0x02050046,
0x02040004,
0x05750003,
0x057409A3,
/* disable EQ first */
0x05350000,
0x0534201A,
/* Left Channel */
0x0535001d,
0x05340800,
0x0535001e,
0x05340800,
0x05350003,
0x05341F7B,
0x05350004,
0x05340000,
/* Right Channel */
0x05450000,
0x05442000,
0x0545001d,
0x05440800,
0x0545001e,
0x05440800,
0x05450003,
0x05441F7B,
0x05450004,
0x05440000,
/* enable EQ */
0x05350000,
0x0534E01A,
/* 1.8W/4ohm */
0x02050038,
0x02047901,
/* AGC Enable */
0x0205004C,
0x0204465C,
0x02050016,
0x02044E50,
0x02050020,
0x020451FF,
/* Headphone Pop */
0x05750007,
0x057412B2,
};
const u32 pc_beep_verbs[] = {
/* Dos beep path - 1 */
0x02050036,
0x02047151,
0x02050010,
0x02040020,
/* Dos beep path - 2 */
0x0143B000,
0x01470740,
0x01470C02,
0x01470C02,
};
AZALIA_ARRAY_SIZES;

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src/mainboard/google/brya/variants/kaladin/include/variant/ec.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __VARIANT_EC_H__
#define __VARIANT_EC_H__
#include <baseboard/ec.h>
#endif

8
src/mainboard/google/brya/variants/kaladin/include/variant/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <baseboard/gpio.h>
#endif

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src/mainboard/google/brya/variants/kaladin/memory.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/variants.h>
#include <gpio.h>
#include <soc/romstage.h>
static const struct mb_cfg variant_memcfg = {
.type = MEM_TYPE_LP5X,
.rcomp = {
/* Baseboard uses only 100ohm Rcomp resistors */
.resistor = 100,
},
/* DQ byte map */
.lpx_dq_map = {
.ddr0 = {
.dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
.dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
},
.ddr1 = {
.dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
.dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
},
.ddr2 = {
.dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
.dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
},
.ddr3 = {
.dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
.dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
},
.ddr4 = {
.dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
.dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
},
.ddr5 = {
.dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
.dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
},
.ddr6 = {
.dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
.dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
},
.ddr7 = {
.dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
.dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
},
},
/* DQS CPU<>DRAM map */
.lpx_dqs_map = {
.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
},
.lp5x_config = {
.ccc_config = 0xff,
},
.ect = 1, /* Early Command Training */
.UserBd = BOARD_TYPE_MOBILE,
};
const struct mb_cfg *variant_memory_params(void)
{
return &variant_memcfg;
}
int variant_memory_sku(void)
{
/*
* Memory configuration board straps
* GPIO_MEM_CONFIG_0 GPP_E1
* GPIO_MEM_CONFIG_1 GPP_E2
* GPIO_MEM_CONFIG_2 GPP_E3
*/
gpio_t spd_gpios[] = {
GPP_E1,
GPP_E2,
GPP_E3,
};
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
}
bool variant_is_half_populated(void)
{
/*
* Ideally half_populated is used in platforms with multiple channels to
* enable only one half of the channel. Alder Lake N has single channel,
* and it would require for new structures to be defined in meminit block
* driver for LPx memory configurations. In order to avoid adding new
* structures, set half_populated to true. This has the same effect as
* having single channel with 64-bit width.
*/
return true;
}
void variant_get_spd_info(struct mem_spd *spd_info)
{
spd_info->topo = MEM_TOPO_MEMORY_DOWN;
spd_info->cbfs_index = variant_memory_sku();
}

9
src/mainboard/google/brya/variants/kaladin/memory/Makefile.mk Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# /tmp/go-build1397538409/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/kaladin/memory/ src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
SPD_SOURCES =
SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9JCNNNBK3MLYR-N6E
SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 1(0b0001) Parts = K3KL6L60GM-MGCT
SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 2(0b0010) Parts = K3KL8L80CM-MGCT

9
src/mainboard/google/brya/variants/kaladin/memory/dram_id.generated.txt Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
# /tmp/go-build1397538409/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/kaladin/memory/ src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt
DRAM Part Name ID to assign
H9JCNNNBK3MLYR-N6E 0 (0000)
K3KL6L60GM-MGCT 1 (0001)
K3KL8L80CM-MGCT 2 (0010)

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src/mainboard/google/brya/variants/kaladin/memory/mem_parts_used.txt Normal file
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# This is a CSV file containing a list of memory parts used by this variant.
# One part per line with an optional fixed ID in column 2.
# Only include a fixed ID if it is required for legacy reasons!
# Generated IDs are dependent on the order of parts in this file,
# so new parts must always be added at the end of the file!
#
# Generate an updated Makefile.mk and dram_id.generated.txt by running the
# part_id_gen tool from util/spd_tools.
# See util/spd_tools/README.md for more details and instructions.
# Part Name
H9JCNNNBK3MLYR-N6E
K3KL6L60GM-MGCT
K3KL8L80CM-MGCT

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src/mainboard/google/brya/variants/kaladin/overridetree.cb Normal file
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fw_config
field THERMAL_SOLUTION 1 1
option THERMAL_SOLUTION_6W 0
option THERMAL_SOLUTION_15W 1
end
field STORAGE 30 31
option STORAGE_EMMC 0
option STORAGE_NVME 1
option STORAGE_UFS 2
option STORAGE_UNKNOWN 3
end
end
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_A"
register "pmc_gpe0_dw1" = "GPP_H"
register "pmc_gpe0_dw2" = "GPP_F"
# S0ix enable
register "s0ix_enable" = "true"
# DPTF enable
register "dptf_enable" = "true"
register "tcc_offset" = "10" # TCC of 90
# Enable CNVi BT
register "cnvi_bt_core" = "true"
# eMMC HS400
register "emmc_enable_hs400_mode" = "true"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch)
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch)
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A MB (6.4 inch)
register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch)
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch)
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3 Type-A port A0(MLB))
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
# SOC Aux orientation override:
# This is a bitfield that corresponds to up to 4 TCSS ports.
# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
# TcssAuxOri = 0101b
# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
# motherboard to USBC connector
register "tcss_aux_ori" = "0"
# HD Audio
register "pch_hda_dsp_enable" = "1"
register "pch_hda_audio_link_hda_enable" = "1"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_codec_enable" = "1"
# Configure external V1P05/Vnn/VnnSx Rails
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
.v1p05_voltage_mv = 1050,
.vnn_voltage_mv = 780,
.vnn_sx_voltage_mv = 1050,
.v1p05_icc_max_ma = 500,
.vnn_icc_max_ma = 500,
}"
# Enable CNVi BT Audio offload
register "cnvi_bt_audio_offload" = "1"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
register "serial_io_gspi_mode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
}"
register "serial_io_uart_mode" = "{
[PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
# FIXME: To be enabled in future based on PNP impact data.
# Disable Package C-state demotion for nissa baseboard.
register "disable_package_c_state_demotion" = "true"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| I2C0 | TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| I2C1 | TouchScreen |
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.early_init = 1,
.speed = I2C_SPEED_FAST_PLUS,
.speed_config[0] = {
.speed = I2C_SPEED_FAST_PLUS,
.scl_lcnt = 55,
.scl_hcnt = 30,
.sda_hold = 7,
}
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 158,
.scl_hcnt = 79,
.sda_hold = 30,
}
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 158,
.scl_hcnt = 79,
.sda_hold = 40,
}
},
}"
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""CPU_VR""
register "options.tsr[1].desc" = ""CPU""
register "options.tsr[2].desc" = ""Ambient""
register "options.tsr[3].desc" = ""Charger""
## Passive Policy
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 85, 4000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 4000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 4000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 4000),
}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN),
}"
register "controls.power_limits" = "{
.pl1 = {
.min_power = 6000,
.max_power = 13000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200
},
.pl2 = {
.min_power = 25000,
.max_power = 25000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000
}
}"
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 4700 },
[1] = { 40, 2500 },
[2] = { 16, 1000 },
[3] = { 8, 500 }
}"
device generic 0 on
probe THERMAL_SOLUTION THERMAL_SOLUTION_6W
end
end
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""CPU_VR""
register "options.tsr[1].desc" = ""CPU""
register "options.tsr[2].desc" = ""Ambient""
register "options.tsr[3].desc" = ""Charger""
## Passive Policy
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 85, 6000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 6000),
}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN),
}"
register "controls.power_limits" = "{
.pl1 = {
.min_power = 15000,
.max_power = 22000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200
},
.pl2 = {
.min_power = 35000,
.max_power = 35000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000
}
}"
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 4700 },
[1] = { 40, 2500 },
[2] = { 16, 1000 },
[3] = { 8, 500 }
}"
device generic 1 on
probe THERMAL_SOLUTION THERMAL_SOLUTION_15W
end
end
end
device ref igpu on
chip drivers/gfx/generic
register "device_count" = "4"
# DDIA for eDP
register "device[0].name" = ""LCD0""
# Internal panel on the first port of the graphics chip
register "device[0].type" = "panel"
# DDIB for HDMI
# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
register "device[1].name" = ""DD01""
# TCP0 (DP-1) for port C0
register "device[2].name" = ""DD02""
register "device[2].use_pld" = "true"
register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
# TCP1 (DP-2) for port C1
register "device[3].name" = ""DD03""
register "device[3].use_pld" = "true"
register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
device generic 0 on end
end
end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
use usb2_port1 as usb2_port
use tcss_usb3_port1 as usb3_port
device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn
use usb2_port2 as usb2_port
use tcss_usb3_port2 as usb3_port
device generic 1 alias conn1 on end
end
end
end
end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
device ref tcss_usb3_port2 on end
end
end
end
end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""PCIe Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
device ref usb2_port8 on
end
end
chip drivers/usb/acpi
register "desc" = ""CNVi Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
device ref usb2_port10 on
end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 WLAN""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb3_port4 on end
end
end
end
end
device ref shared_sram on end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
register "enable_cnvi_ddr_rfim" = "true"
register "add_acpi_dma_property" = "true"
device generic 0 on end
end
end
device ref emmc on end
device ref pcie_rp4 on
# PCIe 4 WLAN
register "pch_pcie_rp[PCH_RP(4)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip drivers/wifi/generic
register "wake" = "GPE0_DW1_03"
register "add_acpi_dma_property" = "true"
device pci 00.0 on end
end
chip soc/intel/common/block/pcie/rtd3
# # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E10)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)"
register "srcclk_pin" = "2"
device generic 0 on end
end
end
device ref pcie_rp11 on
# Enable NVMe SSD PCIE 11-12 using CLK 0
register "pch_pcie_rp[PCH_RP(11)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref i2c0 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
device i2c 50 on end
end
end #I2C0
device ref i2c1 on
chip drivers/i2c/hid
register "generic.hid" = ""ELAN901C""
register "generic.desc" = ""ELAN Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
register "generic.detect" = "1"
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
register "generic.reset_delay_ms" = "20"
register "generic.reset_off_delay_ms" = "2"
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
register "generic.stop_delay_ms" = "280"
register "generic.stop_off_delay_ms" = "2"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 10 on end
end
end #I2C1
device ref i2c5 on
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0000""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
register "generic.wake" = "GPE0_DW2_14"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""SYNA0000""
register "generic.cid" = ""ACPI0C50""
register "generic.desc" = ""Synaptics Touchpad""
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
register "generic.wake" = "GPE0_DW2_14"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x20"
device i2c 0x2c on end
end
end
device ref heci1 on end
device ref ish on
chip drivers/intel/ish
register "add_acpi_dma_property" = "true"
device generic 0 on end
end
end
device ref ufs on end
device ref uart0 on end
device ref pch_espi on
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end
device ref hda on
chip drivers/sof
register "spkr_tplg" = "max98360a"
register "jack_tplg" = "rt5682"
register "mic_tplg" = "_2ch_pdm0"
device generic 0 on end
end
end
end
end