We are gobbling up the `$(CC_$(arch))` stderr when testing the
toolchain. This change makes it so we print the command we tried to
invoke and the output from the command.
```
toolchain.mk:183: The coreboot toolchain for 'x86_32' architecture was not found.
toolchain.mk:183: /build/guybrush/tmp/portage/sys-boot/coreboot-9999/files/reclient/ccache /build/guybrush/tmp/portage/sys-boot/coreboot-9999/work/coreboot-sdk/bin/i386-elf-gcc -v
I AM STDERR
toolchain.mk:183: I AM STDOUT
toolchain.mk:219:
toolchain.mk:220: Path to your toolchain is currently set to '/build/guybrush/tmp/portage/sys-boot/coreboot-9999/work/coreboot-sdk/bin'
toolchain.mk:222:
toolchain.mk:223: To build the entire coreboot toolchain: run 'make crossgcc'
```
BUG=b:392874252, b:389737339
TEST=USE_REMOTEEXEC=true BOARD=brya bazel run @portage//internal/packages/stage2/target/board/chromiumos/sys-boot/coreboot:9999_debug
Change-Id: I7c7352c7254c21deb3e4a03106b841ec9f111ba4
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
All 16 IVB PCIe lanes go to one x16 slot without bifurcation.
There is no use for peg11.
Hide it to squelch the leftover devices warning.
Change-Id: I75402d338e64f477f40682f796477e8fcb94a4e8
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Hide peg12, dev4, and peg60 devices to squelch leftover devices
warning seen with p8z77-m, p8z77-v and p8z77-v_le_plus:
[WARN ] PCI: Leftover static devices:
[WARN ] PCI: 00:00:01.1
[WARN ] PCI: 00:00:01.2
[WARN ] PCI: 00:00:04.0
[WARN ] PCI: 00:00:06.0
[WARN ] PCI: Check your devicetree.cb.
No board in this family can do the 8/4/4 PCIe lane split to
require the peg12 bridge, or implemented dev4 at all.
Only p8c_ws wired up the 4 extra Xeon PCIe lanes peg60 is supposed
to cover, and its overridetree already enables it.
Therefore, be proactive and hide these from the rest of the family.
Change-Id: I24234e6b77a9effc577c8e22c77bb9896b983b7f
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
There is no reason to default to a 1MB CBFS when the descriptor gives us
5MB to work with.
Signed-off-by: Mate Kukri <km@mkukri.xyz>
Change-Id: I65a8b161c522a2da58420397aae6c7ff2b5cf30d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86219
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This is useful when booted with the (not yet mainline) libgfxinit for
Bay Trail.
Signed-off-by: Mate Kukri <km@mkukri.xyz>
Change-Id: I73d54c73a12430074f4f3880caf842b3491b5170
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86218
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Previously only the '06-37-03' and '06-37-09' microcode files were provided
but '06-37-08' was missing.
Linux on my '06-37-08' SOC was segfaulting in various unpredictable ways without
this patch.
Signed-off-by: Mate Kukri <km@mkukri.xyz>
Change-Id: I1a66a8ba980f4fd43f5f54d446edbcd5029e33a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Update dxio descriptors based on PI source code 1.2.0.0a.
Change-Id: I54d35060c34043f9d97658ab84b9b1bb2e62ba60
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit introduces a new macro, cbfs_add_bmp_file, to the ChromeOS
vendor code Makefile. The macro simplifies the process of adding BMP
files to the CBFS (coreboot Filesystem) by encapsulating the
repetitive tasks of specifying file attributes such as file path,
type, and compression flag.
TEST:Both 'cb_logo.bmp' and 'cb_plus_logo.bmp' files are included with
the same properties, within the coreboot firmware image.
Change-Id: I827451da79931c09768965c3ad071ecdd918d367
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
PcieRpLtrEnable[] is a boolean, so use true false.
Change-Id: I4b557683b7897487dedfef0bf77e60b0dab9cbcf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86193
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PcieRpEnable[] is a boolean, so use true false instead of 0 1.
Change-Id: I8e67a33f82b7dfa1864016ccd5cd1b7ec119c528
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
MSEC_TO_USEC(cse_perf_data.timestamp[i]) does overflow.
Here is an example, if cse_perf_data.timestamp[i] value is
4304903 milliseconds. When multiplied by 1000 to convert to
microseconds, the value becomes 0x979B58 instead of 0x100979B58.
TEST=Boot to OS
Change-Id: I09cc00aa595a821a57a34c38a4435e433e935ad3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86215
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add VBT data file for craaskov, and enable its use by selecting
INTEL_GMA_HAVE_VBT.
VBT extracted from stock firmware image Google_Craaskov.15217.616.0;
it has BDB version 2.51, which matches the current FSP binaries.
TEST=build/boot craaskov with edk2 payload
Change-Id: I5854f658b7c8ff421d32b70d43ba8cad94d85b5b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Meteor Lake uses the same helper functon as Alder Lake, so
it can be configured via the opton API.
Change-Id: I6d1dc802e672431aa643e318a7cb045f7d6eaa06
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86239
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an option to selected a reduced brightness for the power LED. The
EC code will use this option to write to the relavant offset
accordingly.
Change-Id: I4796e0572a48bca5f9c59e96466416e975cfe8ca
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Remove the memcpy_s function as it is not used.
Additionally, the function did not return the expected values:
0: If the memory copy is successful.
EINVAL: If dest or src is a null pointer, or if count is greater
than RSIZE_MAX.
ERANGE: If count is greater than destsz.
Change-Id: I0d32c838e94ae760907efe55ed00bab3faaaa8c5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86233
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This GPIO is only used for SATA SSDs so set it as not
connected.
Change-Id: I42c0ec36eee81a849f744a2d03862797f2463921
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The schematic shows that this GPIO is not connected, so
set it as not connected.
Change-Id: Ia62b76055f839c48fc112ca46d8654db5b331cd9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86236
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On boards that do not use SATA, this should be connected.
For boards that do use it, it should be NF5.
Change-Id: I3115627431e80bd5e0f91b53b80fac7c0c95e6f8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86186
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This value used was just wrong; set the correct one that matches
the verb table.
Change-Id: I400d8a4f8472359e5213a1ce9d51a69cde051098
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Explicitly set ECT in romstage; enable it for boards that use
LPxxx memory and disable it for boards that use SODIMMs.
Change-Id: I41bd9b221dc97bb4f76862f7095c20f4b8bc6036
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Correct, and unify, the configuration of the GPIOs use in ACPI
for enabling and resetting:
* Make all GPIOs host owned
* Set enable GPIOs to DEEP
* Set reset GPIOs to PLTRST
Change-Id: I31b49beeb932d9b59b094dcfe182cfc4d91c2562
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86205
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board does not have TBT 4, so unselect Kconfig values
for it.
Change-Id: Id13bb7fc1f9a8f00c10effeaf4b8e1970a173e36
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These pads are required for Audio Offload, so enable them to match
the configuration in devicetree.
Change-Id: I757b2c2f77edb21d0eb1a59e3e1eb81671b9929f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This board is using the USB interface for Bluetooth so these
can be disabled.
Change-Id: I95c3d1607b62c899acdda6b3b3aae97067e6b266
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
BT_EN (VGPIO_0) needs to be host-owned, so that the driver
can control it during the reset procedure. Adjust it accordingly.
Change-Id: I9acc7943de423c0ab441226c0fb4f437a10d2749
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This GPIO is used as MODEM_CLKREQ, which is Native Function 1.
Adjust the configuration accordingly.
Change-Id: If9db29df2a0da71885556a75abcb1da1508a9308
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is proven to be more reliable when resuming from S3.
Change-Id: I479493a384ae1ca880a0caf255ea832b4bb9a366
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86135
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Have two comments, then two blocks of code makes it hard to read.
Seperate them.
Change-Id: I32d6b7c389f64305e8357f52b063628cd99816d6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86196
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On PTL RVP, ISH shares UART with FPS, we can enable either ISH UART or
FPS UART, or disable both UART by changing the DIP switch settings. When
DIP switch is not set for ISH, ISH RX signal is disconnected, causing
ISH low power mode failure. Therefore, NC ISH RX pin mux to minimize the
impact on ISH PM. As a result, ISH console won't accept input since this
pin is not connected.
TEST=PTL RVP H1 DB, DIP SW1317 3-6, 4-5 ON to enable FPS UART, ISH main
firmware boots up and runs successfully.
SW1317 all switches OFF to disable both FPS and ISH UART, ISH main
firmware boots up and runs successfully.
Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a
Signed-off-by: Li Feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86005
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently after UFS is disabled, if the device is coming out of S5 sleep
state then a warm reset is triggered such that PMC samples the UFS
function disable bit and disables the UFS controller accordingly.
Sometimes during the boot flow, an additional kind of reset gets
triggered - Power cycle Reset through CMoff. Hence initiate a warm reset
when the host comes out of S5 sleep state or Power cycle Reset through
CMoff.
BUG=b:391449110
TEST=Build Brox BIOS image and boot to OS. Ensure that when the device
switches from normal mode to developer mode an extra warm reset is
triggered such that the UFS controller is disabled.
Change-Id: I85cad1a1eb00a2a7f520a57cda789ad6737fcb97
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86170
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Introduce an API to read the Converged Security and Management Engine
(CSME) host firmware status register to obtain the current Power
Management event and compare it with a specified input event.
BUG=b:391449110
TEST=Build Brox BIOS image and boot to OS.
Change-Id: Ie9a49382ee2c1a8f59da6233e510cf2e38ac32ad
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86169
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
All of the other targets support invoking the build with the full target
arch name. RISC does not. Update the script to allow riscv64-elf to
invoke the build the same way that riscv-elf does to minimize name
mangling and exceptions needed for tooling surrounding the
architecture name in paths. Leave riscv-elf in tact as an option so
we don't break anyone else.
BUG=None
TEST=./util/crossgcc/buildgcc --platform riscv64-elf
Change-Id: Ie737855053e00205ca85f54436c224ab3a1283d9
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add the printing of the missing libstdcxx path in the warning string
when the path check fails. Also resolve the use of the variable in
the conditional statement by surrounding it with quotes.
BUG=None
TEST=Build with invalid libstdcxx path
Change-Id: I195718e43ea842970f5fa986315c9e9f11395362
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86148
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace PRINT_DEBUG() macro with printram() from device/dram/common.h
for raminit debug messages.
Define a static dummy dump_pci_device() if CONFIG(DEBUG_RAM_SETUP)
is disabled. This allows removing the DUMPNORTH() macro.
dump_spd_registers() will be cleaned up separately.
TEST=Timeless binary remains unchanged.
Change-Id: I685a2f1f38c1afab6a08ff9de4bf82c9061aebec
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This are not used or needed, so remove the configuration for them.
Change-Id: Id422f953dae3157a4ecc61421d246ce1d20019a0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The message printed when duplicate GPE DW register values are
detected was previously logged at the INFO level. This commit
changes the log level to WARNING, as duplicate DW values indicate
a potential misconfiguration and warrant closer attention. While
the system falls back to the default GPE route (as per MISCCFG
register), this situation should be investigated to ensure correct
platform configuration.
This change ensures that developers are more clearly notified of
potential GPE routing issues.
TEST=Built and booted on a platform using PMC GPE routing. Verified
that the message is printed at the WARNING level when duplicate DW
values are present.
Change-Id: I7804ddfa6e067014e034364bd8efbf6efe746cd7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The `pmc_gpe_init` function's check for duplicate GPE DW register values
was incomplete. It only checked for duplicates between DW0 and DW1, and
DW1 and DW2, but failed to check if DW0 and DW2 were the same.
This could lead to incorrect GPE routing if DW0 and DW2 happened to have
the same value, even if DW1 was different.
This commit corrects the check to ensure that all three DW registers
(DW0, DW1, and DW2) are compared against each other. If any two
registers have the same value, a message is printed indicating that
the default GPE route will be used.
Change-Id: I0a52e6aeee619fbc2f712c9c976b067d080ca591
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The `pmc_gpe0_different_values` function previously asserted if any
two of the GPE0 DW registers (DW0, DW1, DW2) had the same value, as
introduced in commit 640a41f3ee ("soc/intel: Assert if
`pmc_/gpe0_dwX` values are not unique"). This prevented platforms from
configuring GPE routing via PMC as per default register (MISCCFG) value.
This commit modifies the check to allow all DW registers to be zero.
This enables platforms that rely on MISCCFG register for
PMC-controlled GPE routing to boot without triggering the assertion.
The change was verified by testing the following scenarios:
- All DWs zero: The system boots using the default GPE route.
No assertion occurs.
- Duplicate DWs (e.g., DW0=1, DW1=2, DW2=2): The existing assertion
is triggered as expected.
- Unique DWs (e.g., DW0=1, DW1=2, DW2=3): No errors occur.
TEST=Built and booted normally. No assertion failure observed.
Change-Id: Ie66d6dbcf49d5400b3fc3e4da113a569fe52dd51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86164
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
