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tree: Use true false for PcieRpEnable[]

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PcieRpEnable[] is a boolean, so use true false instead of 0 1.

Change-Id: I8e67a33f82b7dfa1864016ccd5cd1b7ec119c528
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
This commit is contained in:
Elyes Haouas 2025-01-28 16:34:23 +01:00
commit 7073567051
78 changed files with 370 additions and 370 deletions
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6
src/mainboard/51nb/x210/devicetree.cb
View file

@ -89,7 +89,7 @@ chip soc/intel/skylake
end
device ref pcie_rp3 on
# Ethernet controller
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[2]" = "true"
register "PcieRpClkReqSupport[2]" = "1"
register "PcieRpClkReqNumber[2]" = "0"
register "PcieRpClkSrcNumber[2]" = "0"
@ -98,7 +98,7 @@ chip soc/intel/skylake
end
device ref pcie_rp4 on
# Wireless controller
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[3]" = "true"
register "PcieRpClkReqSupport[3]" = "1"
register "PcieRpClkReqNumber[3]" = "1"
register "PcieRpClkSrcNumber[3]" = "1"
@ -107,7 +107,7 @@ chip soc/intel/skylake
end
device ref pcie_rp9 on
# NVMe controller
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "4"
register "PcieRpClkSrcNumber[8]" = "4"

8
src/mainboard/acer/aspire_vn7_572g/devicetree.cb
View file

@ -251,7 +251,7 @@ chip soc/intel/skylake
# Board has no GPIO expander on I2C4 (despite SetupUtility claim that it does - this would be static text)
device ref pcie_rp1 on
# dGPU; x4
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpClkReqSupport[0]" = "1"
@ -260,7 +260,7 @@ chip soc/intel/skylake
end
device ref pcie_rp7 on
# NGFF; x2
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpAdvancedErrorReporting[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpClkReqSupport[6]" = "1"
@ -269,7 +269,7 @@ chip soc/intel/skylake
end
device ref pcie_rp9 on
# LAN
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpClkReqSupport[8]" = "1"
@ -278,7 +278,7 @@ chip soc/intel/skylake
end
device ref pcie_rp10 on
# WLAN
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[9]" = "true"
register "PcieRpAdvancedErrorReporting[9]" = "1"
register "PcieRpLtrEnable[9]" = "1"
register "PcieRpClkReqSupport[9]" = "1"

8
src/mainboard/asrock/imb-1222/devicetree.cb
View file

@ -209,7 +209,7 @@ chip soc/intel/cannonlake
}"
end
device ref pcie_rp17 on # M.2 Key-M 2242/2260/2280 slot for SSD (PCIEx4)
register "PcieRpEnable[16]" = "1"
register "PcieRpEnable[16]" = "true"
register "PcieRpLtrEnable[16]" = "1"
register "PcieRpSlotImplemented[16]" = "1"
register "PcieClkSrcUsage[7]" = "16"
@ -217,13 +217,13 @@ chip soc/intel/cannonlake
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2242/2260/2280 (M2_KEYM1)" "SlotDataBusWidth4X"
end
device ref pcie_rp5 on # Intel Corporation Ethernet Controller I225-LM
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieClkSrcUsage[3]" = "4"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp6 on # M.2 Key-E 2230 slot for Wireless M.2 Key-E (PCIe x1)
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieRpSlotImplemented[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieClkSrcUsage[5]" = "5"
@ -231,7 +231,7 @@ chip soc/intel/cannonlake
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (M2_KEYE1)" "SlotDataBusWidth1X"
end
device ref pcie_rp7 on # M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1)
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpSlotImplemented[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieClkSrcUsage[6]" = "6"

8
src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
View file

@ -112,7 +112,7 @@ chip soc/intel/cannonlake
device ref uart2 on end
device ref pcie_rp6 on
device pci 00.0 on end # x1 Card reader
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieRpLtrEnable[5]" = "1"
register "PcieClkSrcUsage[3]" = "5"
register "PcieClkSrcClkReq[3]" = "3"
@ -121,7 +121,7 @@ chip soc/intel/cannonlake
chip drivers/wifi/generic
device pci 00.0 on end
end
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
register "PcieClkSrcUsage[2]" = "7"
register "PcieClkSrcClkReq[2]" = "2"
@ -129,7 +129,7 @@ chip soc/intel/cannonlake
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
end
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[4]" = "8"
register "PcieClkSrcClkReq[4]" = "4"
@ -137,7 +137,7 @@ chip soc/intel/cannonlake
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
end
device ref pcie_rp13 on
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"

8
src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
View file

@ -66,7 +66,7 @@ chip soc/intel/skylake
device ref uart2 on end
device ref pcie_rp1 on
device pci 00.0 on end # x4 TBT
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "4"
register "PcieRpClkSrcNumber[0]" = "4"
@ -76,7 +76,7 @@ chip soc/intel/skylake
end
device ref pcie_rp5 on
device pci 00.0 on end # x1 LAN
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "3"
register "PcieRpClkSrcNumber[4]" = "3"
@ -84,7 +84,7 @@ chip soc/intel/skylake
end
device ref pcie_rp6 on
device pci 00.0 on end # x1 WLAN
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieRpClkReqSupport[5]" = "1"
register "PcieRpClkReqNumber[5]" = "2"
register "PcieRpClkSrcNumber[5]" = "2"
@ -93,7 +93,7 @@ chip soc/intel/skylake
end
device ref pcie_rp9 on
device pci 00.0 on end # x4 M.2/M (J_SSD1)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "5"
register "PcieRpClkSrcNumber[8]" = "5"

6
src/mainboard/facebook/monolith/devicetree.cb
View file

@ -157,7 +157,7 @@ chip soc/intel/skylake
device ref pcie_rp3 on
# x1 baseboard WWAN
# PCIE Port 3 x1 -> Module x1 : Mapped to PCIe 2 on the baseboard
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[2]" = "true"
register "PcieRpClkReqSupport[2]" = "0"
register "PcieRpMaxPayload[2]" = "RpMaxPayload_256"
register "PcieRpLtrEnable[2]" = "1"
@ -167,7 +167,7 @@ chip soc/intel/skylake
device ref pcie_rp6 on
# x1 baseboard i210
# PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieRpClkReqSupport[5]" = "0"
register "PcieRpMaxPayload[5]" = "RpMaxPayload_256"
register "PcieRpLtrEnable[5]" = "1"
@ -177,7 +177,7 @@ chip soc/intel/skylake
device ref pcie_rp9 on
# x4 FPGA
# PCIE Port 9 x4 -> BASEBOARD PEG0-3 FPGA
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "0"
register "PcieRpHotPlug[8]" = "1"
register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"

4
src/mainboard/google/drallion/variants/drallion/devicetree.cb
View file

@ -193,13 +193,13 @@ chip soc/intel/cannonlake
}"
# PCIe port 9 for Card Reader
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[4]" = "8"
register "PcieClkSrcClkReq[4]" = "4"
# PCIe port 13 for M.2 2280 SSD
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[2]" = "12"
register "PcieClkSrcClkReq[2]" = "2"

4
src/mainboard/google/eve/devicetree.cb
View file

@ -336,7 +336,7 @@ chip soc/intel/skylake
end
end # I2C #4
device ref pcie_rp1 on
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
@ -349,7 +349,7 @@ chip soc/intel/skylake
end
end
device ref pcie_rp5 on
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "4"
register "PcieRpAdvancedErrorReporting[4]" = "1"

12
src/mainboard/google/fizz/variants/baseboard/devicetree.cb
View file

@ -289,7 +289,7 @@ chip soc/intel/skylake
device ref pcie_rp3 on
# LAN, will be swapped to port 1 by FSP
# x1
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[2]" = "true"
register "PcieRpClkReqSupport[2]" = "1"
register "PcieRpClkReqNumber[2]" = "0"
register "PcieRpAdvancedErrorReporting[2]" = "1"
@ -304,7 +304,7 @@ chip soc/intel/skylake
end
device ref pcie_rp4 on
# x1 WLAN
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[3]" = "true"
register "PcieRpClkReqSupport[3]" = "1"
register "PcieRpClkReqNumber[3]" = "5"
register "PcieRpAdvancedErrorReporting[3]" = "1"
@ -317,7 +317,7 @@ chip soc/intel/skylake
end
device ref pcie_rp5 on
# x4 NVMe
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "1"
register "PcieRpAdvancedErrorReporting[4]" = "1"
@ -326,7 +326,7 @@ chip soc/intel/skylake
end
device ref pcie_rp9 on
# 2nd LAN
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "2"
register "PcieRpAdvancedErrorReporting[8]" = "1"
@ -339,7 +339,7 @@ chip soc/intel/skylake
end
end
device ref pcie_rp11 on
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpClkReqSupport[10]" = "1"
register "PcieRpClkReqNumber[10]" = "2"
register "PcieRpAdvancedErrorReporting[10]" = "1"
@ -347,7 +347,7 @@ chip soc/intel/skylake
register "PcieRpClkSrcNumber[10]" = "2"
end
device ref pcie_rp12 on
register "PcieRpEnable[11]" = "1"
register "PcieRpEnable[11]" = "true"
register "PcieRpClkReqSupport[11]" = "1"
register "PcieRpClkReqNumber[11]" = "2"
register "PcieRpAdvancedErrorReporting[11]" = "1"

12
src/mainboard/google/fizz/variants/endeavour/overridetree.cb
View file

@ -116,7 +116,7 @@ chip soc/intel/skylake
end
device ref pcie_rp7 on
# x1 TPU1
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpClkReqSupport[6]" = "1"
register "PcieRpClkReqNumber[6]" = "4"
register "PcieRpAdvancedErrorReporting[6]" = "1"
@ -125,7 +125,7 @@ chip soc/intel/skylake
end
device ref pcie_rp8 on
# x1 TPU0
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieRpClkReqSupport[7]" = "1"
register "PcieRpClkReqNumber[7]" = "2"
register "PcieRpAdvancedErrorReporting[7]" = "1"
@ -134,20 +134,20 @@ chip soc/intel/skylake
end
device ref pcie_rp9 on
# x4 i350 LAN
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "0"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpClkSrcNumber[8]" = "2"
end
device ref pcie_rp10 off
register "PcieRpEnable[9]" = "0"
register "PcieRpEnable[9]" = "false"
end
device ref pcie_rp11 off
register "PcieRpEnable[10]" = "0"
register "PcieRpEnable[10]" = "false"
end
device ref pcie_rp12 off
register "PcieRpEnable[11]" = "0"
register "PcieRpEnable[11]" = "false"
end
end
end

2
src/mainboard/google/glados/devicetree.cb
View file

@ -78,7 +78,7 @@ chip soc/intel/skylake
device ref uart2 on end
device ref i2c4 on end
device ref pcie_rp1 on
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
chip drivers/wifi/generic

4
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View file

@ -162,7 +162,7 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
# Enable Root port 9(x4) for NVMe.
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
@ -170,7 +170,7 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[1]" = "1"
# PCIe port 14 for M.2 E-key WLAN
register "PcieRpEnable[13]" = "1"
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
# RP 14 uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "13"

2
src/mainboard/google/hatch/variants/helios/overridetree.cb
View file

@ -20,7 +20,7 @@ chip soc/intel/cannonlake
}"
# No PCIe WiFi
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[13]" = "false"
# Intel Common SoC Config
#+-------------------+---------------------------+

6
src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
View file

@ -20,7 +20,7 @@ chip soc/intel/cannonlake
}"
# Enable Root port 9(x2) for NVMe.
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
@ -28,7 +28,7 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[1]" = "1"
# Enable Root port 11(x2) for NVMe.
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
# RP 11 uses CLK SRC 2
register "PcieClkSrcUsage[2]" = "10"
@ -36,7 +36,7 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[2]" = "1"
# No PCIe WiFi
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[13]" = "false"
# Intel Common SoC Config
#+-------------------+---------------------------+

2
src/mainboard/google/hatch/variants/kohaku/overridetree.cb
View file

@ -20,7 +20,7 @@ chip soc/intel/cannonlake
}"
# No PCIe WiFi
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[13]" = "false"
# Enable DMIC1
register "PchHdaAudioLinkDmic1" = "1"

4
src/mainboard/google/hatch/variants/mushu/overridetree.cb
View file

@ -71,14 +71,14 @@ chip soc/intel/cannonlake
}"
# PCIe port 7 for M.2 E-key WLAN
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
# RP 7 uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "6"
register "PcieClkSrcClkReq[3]" = "3"
# Enable Root port 13 (x4) for dGPU
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
# RP 13 uses CLK SRC 5
register "PcieClkSrcUsage[5]" = "12"

2
src/mainboard/google/hatch/variants/nightfury/overridetree.cb
View file

@ -20,7 +20,7 @@ chip soc/intel/cannonlake
}"
# No PCIe WiFi
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[13]" = "false"
# Enable DMIC1
register "PchHdaAudioLinkDmic1" = "1"

2
src/mainboard/google/hatch/variants/palkia/overridetree.cb
View file

@ -23,7 +23,7 @@ chip soc/intel/cannonlake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD
# No PCIe WiFi
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[13]" = "false"
# Intel Common SoC Config
#+-------------------+---------------------------+

2
src/mainboard/google/poppy/variants/atlas/devicetree.cb
View file

@ -310,7 +310,7 @@ chip soc/intel/skylake
end
device ref pcie_rp1 on
# WLAN
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkSrcNumber[0]" = "1"

2
src/mainboard/google/poppy/variants/baseboard/devicetree.cb
View file

@ -323,7 +323,7 @@ chip soc/intel/skylake
end
device ref i2c4 on end
device ref pcie_rp1 on
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"

6
src/mainboard/google/poppy/variants/nami/devicetree.cb
View file

@ -366,7 +366,7 @@ chip soc/intel/skylake
device ref pcie_rp1 on end
device ref pcie_rp4 on
# x1
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[3]" = "true"
register "PcieRpClkReqSupport[3]" = "1"
register "PcieRpClkReqNumber[3]" = "1"
register "PcieRpClkSrcNumber[3]" = "1"
@ -379,7 +379,7 @@ chip soc/intel/skylake
end
device ref pcie_rp5 on
# x4
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "3"
register "PcieRpClkSrcNumber[4]" = "3"
@ -388,7 +388,7 @@ chip soc/intel/skylake
end
device ref pcie_rp9 on
# x2
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "2"
register "PcieRpClkSrcNumber[8]" = "2"

2
src/mainboard/google/poppy/variants/nautilus/devicetree.cb
View file

@ -361,7 +361,7 @@ chip soc/intel/skylake
end
end
device ref pcie_rp1 on
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkSrcNumber[0]" = "1"

4
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View file

@ -325,7 +325,7 @@ chip soc/intel/skylake
end
end
device ref pcie_rp1 on
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkSrcNumber[0]" = "1"
@ -338,7 +338,7 @@ chip soc/intel/skylake
end
device ref pcie_rp9 on
# x2
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "2"
register "PcieRpClkSrcNumber[8]" = "3"

2
src/mainboard/google/poppy/variants/rammus/devicetree.cb
View file

@ -314,7 +314,7 @@ chip soc/intel/skylake
end
end
device ref pcie_rp1 on
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpClkSrcNumber[0]" = "1"

2
src/mainboard/google/poppy/variants/soraka/devicetree.cb
View file

@ -305,7 +305,7 @@ chip soc/intel/skylake
end
device ref i2c4 on end
device ref pcie_rp1 on
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"

4
src/mainboard/google/puff/variants/ambassador/overridetree.cb
View file

@ -184,10 +184,10 @@ chip soc/intel/cannonlake
}"
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"

4
src/mainboard/google/puff/variants/baseboard/devicetree.cb
View file

@ -162,7 +162,7 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
# Enable Root port 9(x4) for NVMe.
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
@ -170,7 +170,7 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[1]" = "1"
# PCIe port 14 for M.2 E-key WLAN
register "PcieRpEnable[13]" = "1"
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
# RP 14 uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "13"

2
src/mainboard/google/puff/variants/dooly/overridetree.cb
View file

@ -173,7 +173,7 @@ chip soc/intel/cannonlake
}"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"

4
src/mainboard/google/puff/variants/duffy/overridetree.cb
View file

@ -245,10 +245,10 @@ chip soc/intel/cannonlake
}"
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"

4
src/mainboard/google/puff/variants/faffy/overridetree.cb
View file

@ -253,10 +253,10 @@ chip soc/intel/cannonlake
}"
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"

20
src/mainboard/google/puff/variants/genesis/overridetree.cb
View file

@ -177,45 +177,45 @@ chip soc/intel/cannonlake
}"
# PCIe root port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port 8 for WLAN
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
# Uses CLK SRC 5
register "PcieClkSrcUsage[5]" = "7"
register "PcieClkSrcClkReq[5]" = "5"
# PCIe root port 9 for SSD (PCIe Lanes 11, 12)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
register "PcieClkSrcClkReq[1]" = "1"
# PCIe root port 10 disabled
register "PcieRpEnable[9]" = "0"
register "PcieRpEnable[9]" = "false"
# PCIe root port 11 TPU1
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
# RP 11 uses CLK SRC 1
register "PcieClkSrcUsage[4]" = "10"
register "PcieClkSrcClkReq[4]" = "4"
# PCIe root port 12 TPU0
register "PcieRpEnable[11]" = "1"
register "PcieRpEnable[11]" = "true"
register "PcieRpLtrEnable[11]" = "1"
# RP 11 uses CLK SRC 1
register "PcieClkSrcUsage[2]" = "11"
register "PcieClkSrcClkReq[2]" = "2"
# PCIe port 13 for i350 NIC (x4)
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
# RP 13 uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "12"
@ -224,9 +224,9 @@ chip soc/intel/cannonlake
# effectively "not connected"
register "PcieClkSrcClkReq[3]" = "0xFF"
# Disable the remaining ports 14-16
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[14]" = "0"
register "PcieRpEnable[15]" = "0"
register "PcieRpEnable[13]" = "false"
register "PcieRpEnable[14]" = "false"
register "PcieRpEnable[15]" = "false"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "vSD3_CD_B"

4
src/mainboard/google/puff/variants/kaisa/overridetree.cb
View file

@ -245,10 +245,10 @@ chip soc/intel/cannonlake
}"
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"

20
src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
View file

@ -177,45 +177,45 @@ chip soc/intel/cannonlake
}"
# PCIe root port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port 8 for WLAN
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
# Uses CLK SRC 5
register "PcieClkSrcUsage[5]" = "7"
register "PcieClkSrcClkReq[5]" = "5"
# PCIe root port 9 for SSD (PCIe Lanes 11, 12)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
register "PcieClkSrcClkReq[1]" = "1"
# PCIe root port 10 disabled
register "PcieRpEnable[9]" = "0"
register "PcieRpEnable[9]" = "false"
# PCIe root port 11 TPU1
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
# RP 11 uses CLK SRC 1
register "PcieClkSrcUsage[4]" = "10"
register "PcieClkSrcClkReq[4]" = "4"
# PCIe root port 12 TPU0
register "PcieRpEnable[11]" = "1"
register "PcieRpEnable[11]" = "true"
register "PcieRpLtrEnable[11]" = "1"
# RP 11 uses CLK SRC 1
register "PcieClkSrcUsage[2]" = "11"
register "PcieClkSrcClkReq[2]" = "2"
# PCIe port 13 for i350 NIC (x4)
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
# RP 13 uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "12"
@ -224,9 +224,9 @@ chip soc/intel/cannonlake
# effectively "not connected"
register "PcieClkSrcClkReq[3]" = "0xFF"
# Disable the remaining ports 14-16
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[14]" = "0"
register "PcieRpEnable[15]" = "0"
register "PcieRpEnable[13]" = "false"
register "PcieRpEnable[14]" = "false"
register "PcieRpEnable[15]" = "false"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "vSD3_CD_B"

4
src/mainboard/google/puff/variants/noibat/overridetree.cb
View file

@ -168,10 +168,10 @@ chip soc/intel/cannonlake
}"
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"

4
src/mainboard/google/puff/variants/puff/overridetree.cb
View file

@ -178,10 +178,10 @@ chip soc/intel/cannonlake
}"
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"

20
src/mainboard/google/puff/variants/scout/overridetree.cb
View file

@ -184,47 +184,47 @@ chip soc/intel/cannonlake
}"
# PCIe root port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"
register "PcieClkSrcClkReq[0]" = "0"
# PCIe root port 8 for WLAN
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
# Uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcClkReq[3]" = "3"
# PCIe root port 9 for SSD (PCIe Lanes 9-12)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
# RP 9 uses CLK SRC 1
register "PcieClkSrcUsage[1]" = "8"
register "PcieClkSrcClkReq[1]" = "1"
# PCIe root port 10-12 disabled
register "PcieRpEnable[9]" = "0"
register "PcieRpEnable[10]" = "0"
register "PcieRpEnable[11]" = "0"
register "PcieRpEnable[9]" = "false"
register "PcieRpEnable[10]" = "false"
register "PcieRpEnable[11]" = "false"
# PCIe root port 13 TPU0
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
# RP 13 uses CLK SRC 2
register "PcieClkSrcUsage[2]" = "12"
register "PcieClkSrcClkReq[2]" = "2"
# PCIe root port 14 TPU1
register "PcieRpEnable[13]" = "1"
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
# RP 14 uses CLK SRC 4
register "PcieClkSrcUsage[4]" = "13"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieRpEnable[14]" = "0"
register "PcieRpEnable[15]" = "0"
register "PcieRpEnable[14]" = "false"
register "PcieRpEnable[15]" = "false"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "vSD3_CD_B"

4
src/mainboard/google/puff/variants/wyvern/overridetree.cb
View file

@ -179,10 +179,10 @@ chip soc/intel/cannonlake
}"
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"

6
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View file

@ -182,18 +182,18 @@ chip soc/intel/cannonlake
}"
# PCIe port 10 for M.2 2230 WLAN
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[9]" = "true"
register "PcieClkSrcUsage[2]" = "9"
register "PcieClkSrcClkReq[2]" = "2"
# PCIe port 11 for card reader
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieClkSrcUsage[1]" = "10"
register "PcieClkSrcClkReq[1]" = "1"
# PCIe port 13 for M.2 2280 SSD
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[4]" = "12"
register "PcieClkSrcClkReq[4]" = "4"

8
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View file

@ -182,23 +182,23 @@ chip soc/intel/cannonlake
}"
# PCIe port 8 for Card Reader
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
register "PcieClkSrcUsage[4]" = "7"
register "PcieClkSrcClkReq[4]" = "4"
# PCIe port 9 for LAN
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN"
register "PcieClkSrcClkReq[3]" = "3"
# PCIe port 10 for M.2 2230 WLAN
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[9]" = "true"
register "PcieClkSrcUsage[1]" = "9"
register "PcieClkSrcClkReq[1]" = "1"
# PCIe port 13 for M.2 2280 SSD
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[2]" = "12"
register "PcieClkSrcClkReq[2]" = "2"

48
src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
View file

@ -42,30 +42,30 @@ chip soc/intel/cannonlake
register "PchHdaDspEnable" = "0"
register "PchHdaAudioLinkHda" = "1"
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[5]" = "0"
register "PcieRpEnable[6]" = "0"
register "PcieRpEnable[7]" = "0"
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[11]" = "1"
register "PcieRpEnable[12]" = "0"
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[14]" = "0"
register "PcieRpEnable[15]" = "0"
register "PcieRpEnable[16]" = "0"
register "PcieRpEnable[17]" = "0"
register "PcieRpEnable[18]" = "0"
register "PcieRpEnable[19]" = "0"
register "PcieRpEnable[20]" = "0"
register "PcieRpEnable[21]" = "0"
register "PcieRpEnable[22]" = "0"
register "PcieRpEnable[23]" = "0"
register "PcieRpEnable[0]" = "true"
register "PcieRpEnable[1]" = "true"
register "PcieRpEnable[2]" = "true"
register "PcieRpEnable[3]" = "true"
register "PcieRpEnable[4]" = "true"
register "PcieRpEnable[5]" = "false"
register "PcieRpEnable[6]" = "false"
register "PcieRpEnable[7]" = "false"
register "PcieRpEnable[8]" = "true"
register "PcieRpEnable[9]" = "true"
register "PcieRpEnable[10]" = "true"
register "PcieRpEnable[11]" = "true"
register "PcieRpEnable[12]" = "false"
register "PcieRpEnable[13]" = "false"
register "PcieRpEnable[14]" = "false"
register "PcieRpEnable[15]" = "false"
register "PcieRpEnable[16]" = "false"
register "PcieRpEnable[17]" = "false"
register "PcieRpEnable[18]" = "false"
register "PcieRpEnable[19]" = "false"
register "PcieRpEnable[20]" = "false"
register "PcieRpEnable[21]" = "false"
register "PcieRpEnable[22]" = "false"
register "PcieRpEnable[23]" = "false"
register "PcieClkSrcUsage[0]" = "1"
register "PcieClkSrcUsage[1]" = "8"

48
src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
View file

@ -40,30 +40,30 @@ chip soc/intel/cannonlake
register "PchHdaDspEnable" = "0"
register "PchHdaAudioLinkHda" = "1"
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[5]" = "0"
register "PcieRpEnable[6]" = "0"
register "PcieRpEnable[7]" = "0"
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[9]" = "0"
register "PcieRpEnable[10]" = "0"
register "PcieRpEnable[11]" = "0"
register "PcieRpEnable[12]" = "0"
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[14]" = "0"
register "PcieRpEnable[15]" = "0"
register "PcieRpEnable[16]" = "1"
register "PcieRpEnable[17]" = "1"
register "PcieRpEnable[18]" = "1"
register "PcieRpEnable[19]" = "1"
register "PcieRpEnable[20]" = "1"
register "PcieRpEnable[21]" = "1"
register "PcieRpEnable[22]" = "1"
register "PcieRpEnable[23]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpEnable[1]" = "true"
register "PcieRpEnable[2]" = "true"
register "PcieRpEnable[3]" = "true"
register "PcieRpEnable[4]" = "true"
register "PcieRpEnable[5]" = "false"
register "PcieRpEnable[6]" = "false"
register "PcieRpEnable[7]" = "false"
register "PcieRpEnable[8]" = "true"
register "PcieRpEnable[9]" = "false"
register "PcieRpEnable[10]" = "false"
register "PcieRpEnable[11]" = "false"
register "PcieRpEnable[12]" = "false"
register "PcieRpEnable[13]" = "false"
register "PcieRpEnable[14]" = "false"
register "PcieRpEnable[15]" = "false"
register "PcieRpEnable[16]" = "true"
register "PcieRpEnable[17]" = "true"
register "PcieRpEnable[18]" = "true"
register "PcieRpEnable[19]" = "true"
register "PcieRpEnable[20]" = "true"
register "PcieRpEnable[21]" = "true"
register "PcieRpEnable[22]" = "true"
register "PcieRpEnable[23]" = "true"
register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[1]" = "8"

32
src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
View file

@ -3,22 +3,22 @@ chip soc/intel/cannonlake
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHda" = "1"
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[5]" = "0"
register "PcieRpEnable[6]" = "0"
register "PcieRpEnable[7]" = "0"
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[9]" = "0"
register "PcieRpEnable[10]" = "0"
register "PcieRpEnable[11]" = "0"
register "PcieRpEnable[12]" = "0"
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[14]" = "0"
register "PcieRpEnable[15]" = "0"
register "PcieRpEnable[0]" = "true"
register "PcieRpEnable[1]" = "true"
register "PcieRpEnable[2]" = "true"
register "PcieRpEnable[3]" = "true"
register "PcieRpEnable[4]" = "true"
register "PcieRpEnable[5]" = "false"
register "PcieRpEnable[6]" = "false"
register "PcieRpEnable[7]" = "false"
register "PcieRpEnable[8]" = "true"
register "PcieRpEnable[9]" = "false"
register "PcieRpEnable[10]" = "false"
register "PcieRpEnable[11]" = "false"
register "PcieRpEnable[12]" = "false"
register "PcieRpEnable[13]" = "false"
register "PcieRpEnable[14]" = "false"
register "PcieRpEnable[15]" = "false"
register "PcieClkSrcUsage[0]" = "1"
register "PcieClkSrcUsage[1]" = "8"

32
src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
View file

@ -41,22 +41,22 @@ chip soc/intel/cannonlake
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHda" = "1"
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[5]" = "0"
register "PcieRpEnable[6]" = "0"
register "PcieRpEnable[7]" = "0"
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[9]" = "0"
register "PcieRpEnable[10]" = "0"
register "PcieRpEnable[11]" = "0"
register "PcieRpEnable[12]" = "0"
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[14]" = "0"
register "PcieRpEnable[15]" = "0"
register "PcieRpEnable[0]" = "true"
register "PcieRpEnable[1]" = "true"
register "PcieRpEnable[2]" = "true"
register "PcieRpEnable[3]" = "true"
register "PcieRpEnable[4]" = "true"
register "PcieRpEnable[5]" = "false"
register "PcieRpEnable[6]" = "false"
register "PcieRpEnable[7]" = "false"
register "PcieRpEnable[8]" = "true"
register "PcieRpEnable[9]" = "false"
register "PcieRpEnable[10]" = "false"
register "PcieRpEnable[11]" = "false"
register "PcieRpEnable[12]" = "false"
register "PcieRpEnable[13]" = "false"
register "PcieRpEnable[14]" = "false"
register "PcieRpEnable[15]" = "false"
register "PcieClkSrcUsage[0]" = "1"
register "PcieClkSrcUsage[1]" = "8"

32
src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
View file

@ -26,22 +26,22 @@ chip soc/intel/cannonlake
register "PchHdaDspEnable" = "1"
register "PchHdaAudioLinkHda" = "1"
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[5]" = "0"
register "PcieRpEnable[6]" = "0"
register "PcieRpEnable[7]" = "0"
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[9]" = "0"
register "PcieRpEnable[10]" = "0"
register "PcieRpEnable[11]" = "0"
register "PcieRpEnable[12]" = "0"
register "PcieRpEnable[13]" = "0"
register "PcieRpEnable[14]" = "0"
register "PcieRpEnable[15]" = "0"
register "PcieRpEnable[0]" = "true"
register "PcieRpEnable[1]" = "true"
register "PcieRpEnable[2]" = "true"
register "PcieRpEnable[3]" = "true"
register "PcieRpEnable[4]" = "true"
register "PcieRpEnable[5]" = "false"
register "PcieRpEnable[6]" = "false"
register "PcieRpEnable[7]" = "false"
register "PcieRpEnable[8]" = "true"
register "PcieRpEnable[9]" = "false"
register "PcieRpEnable[10]" = "false"
register "PcieRpEnable[11]" = "false"
register "PcieRpEnable[12]" = "false"
register "PcieRpEnable[13]" = "false"
register "PcieRpEnable[14]" = "false"
register "PcieRpEnable[15]" = "false"
register "PcieClkSrcUsage[0]" = "1"
register "PcieClkSrcUsage[1]" = "8"

12
src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
View file

@ -75,37 +75,37 @@ chip soc/intel/skylake
end
device ref i2c4 off end
device ref pcie_rp6 on
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieRpClkReqSupport[5]" = "1"
register "PcieRpClkReqNumber[5]" = "1"
register "PcieRpClkSrcNumber[5]" = "1"
end
device ref pcie_rp7 on
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpClkReqSupport[6]" = "1"
register "PcieRpClkReqNumber[6]" = "2"
register "PcieRpClkSrcNumber[6]" = "2"
end
device ref pcie_rp8 on
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieRpClkReqSupport[7]" = "1"
register "PcieRpClkReqNumber[7]" = "3"
register "PcieRpClkSrcNumber[7]" = "3"
end
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "4"
register "PcieRpClkSrcNumber[8]" = "4"
end
device ref pcie_rp14 on
register "PcieRpEnable[13]" = "1"
register "PcieRpEnable[13]" = "true"
register "PcieRpClkReqSupport[13]" = "1"
register "PcieRpClkReqNumber[13]" = "5"
register "PcieRpClkSrcNumber[13]" = "5"
end
device ref pcie_rp17 on
register "PcieRpEnable[16]" = "1"
register "PcieRpEnable[16]" = "true"
register "PcieRpClkReqSupport[16]" = "1"
register "PcieRpClkReqNumber[16]" = "7"
register "PcieRpClkSrcNumber[16]" = "7"

10
src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
View file

@ -77,35 +77,35 @@ chip soc/intel/skylake
device ref cio on end
device ref pcie_rp1 on
# PCIE x4 -> SLOT1
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "2"
register "PcieRpClkSrcNumber[0]" = "2"
end
device ref pcie_rp5 on
# PCIE x1 -> SLOT2/LAN
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "3"
register "PcieRpClkSrcNumber[4]" = "3"
end
device ref pcie_rp6 on
# PCIE x1 -> SLOT3
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieRpClkReqSupport[5]" = "1"
register "PcieRpClkReqNumber[5]" = "1"
register "PcieRpClkSrcNumber[5]" = "1"
end
device ref pcie_rp9 on
# PCIE x1 -> WLAN
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "5"
register "PcieRpClkSrcNumber[8]" = "5"
end
device ref pcie_rp10 on
# PCIE x1 -> WiGig
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[9]" = "true"
register "PcieRpClkReqSupport[9]" = "1"
register "PcieRpClkReqNumber[9]" = "4"
register "PcieRpClkSrcNumber[9]" = "4"

10
src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
View file

@ -124,31 +124,31 @@ chip soc/intel/skylake
}"
end
device ref pcie_rp3 on
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[2]" = "true"
register "PcieRpClkReqSupport[2]" = "1"
register "PcieRpClkReqNumber[2]" = "5"
register "PcieRpClkSrcNumber[2]" = "5"
end
device ref pcie_rp4 on
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[3]" = "true"
register "PcieRpClkReqSupport[3]" = "1"
register "PcieRpClkReqNumber[3]" = "2"
register "PcieRpClkSrcNumber[3]" = "2"
end
device ref pcie_rp5 on
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "3"
register "PcieRpClkSrcNumber[4]" = "3"
end
device ref pcie_rp6 on
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieRpClkReqSupport[5]" = "1"
register "PcieRpClkReqNumber[5]" = "4"
register "PcieRpClkSrcNumber[5]" = "4"
end
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "1"
register "PcieRpClkSrcNumber[8]" = "1"

8
src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
View file

@ -148,22 +148,22 @@ chip soc/intel/skylake
device ref pcie_rp1 off end
device ref pcie_rp3 on end
device ref pcie_rp4 on
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[3]" = "true"
register "PcieRpClkReqSupport[3]" = "1"
register "PcieRpClkReqNumber[3]" = "2"
end
device ref pcie_rp5 on
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "1"
end
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "6"
end
device ref pcie_rp17 on
register "PcieRpEnable[16]" = "1"
register "PcieRpEnable[16]" = "true"
register "PcieRpClkReqSupport[16]" = "1"
register "PcieRpClkReqNumber[16]" = "7"
end

4
src/mainboard/intel/kunimitsu/devicetree.cb
View file

@ -210,7 +210,7 @@ chip soc/intel/skylake
end
end
device ref pcie_rp1 on
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "1"
chip drivers/wifi/generic
@ -219,7 +219,7 @@ chip soc/intel/skylake
end
end
device ref pcie_rp5 on
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "2"
end

8
src/mainboard/intel/saddlebrook/devicetree.cb
View file

@ -186,24 +186,24 @@ chip soc/intel/skylake
device ref i2c4 on end
device ref pcie_rp1 on end
device ref pcie_rp6 on
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieRpClkReqSupport[5]" = "1"
register "PcieRpClkReqNumber[5]" = "0"
end
device ref pcie_rp8 on
# x1
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieRpClkReqSupport[7]" = "1"
register "PcieRpClkReqNumber[7]" = "3"
end
device ref pcie_rp9 on
# x4
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "4"
end
device ref pcie_rp13 on
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpClkReqSupport[12]" = "1"
register "PcieRpClkReqNumber[12]" = "1"
end

6
src/mainboard/kontron/bsl6/devicetree.cb
View file

@ -86,13 +86,13 @@ chip soc/intel/skylake
}"
end
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
end
device ref pcie_rp10 on
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[9]" = "true"
end
device ref pcie_rp11 on
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"

10
src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb
View file

@ -22,23 +22,23 @@ chip soc/intel/skylake
end
device ref pcie_rp1 on
# COMe 4
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
end
device ref pcie_rp2 on
# COMe 5
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[1]" = "true"
end
device ref pcie_rp3 on
# COMe 6
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[2]" = "true"
end
device ref pcie_rp4 on
# COMe 7
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[3]" = "true"
end
device ref pcie_rp12 on
# COMe 3
register "PcieRpEnable[11]" = "1"
register "PcieRpEnable[11]" = "true"
end
device ref smbus on
chip drivers/i2c/nct7802y

4
src/mainboard/libretrend/lt1000/devicetree.cb
View file

@ -165,11 +165,11 @@ chip soc/intel/skylake
register "PcieRpClkSrcNumber[9]" = "3"
end
device ref pcie_rp11 on
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpClkSrcNumber[10]" = "3"
end
device ref pcie_rp12 on
register "PcieRpEnable[11]" = "1"
register "PcieRpEnable[11]" = "true"
register "PcieRpClkSrcNumber[11]" = "3"
end
device ref lpc_espi on

20
src/mainboard/prodrive/hermes/devicetree.cb
View file

@ -171,7 +171,7 @@ chip soc/intel/cannonlake
device ref uart2 hidden end # in ACPI mode
device ref pcie_rp21 on
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
register "PcieRpEnable[20]" = "1"
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieRpSlotImplemented[20]" = "1"
register "PcieRpMaxPayload[20]" = "RpMaxPayload_256"
@ -180,7 +180,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp1 on
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpSlotImplemented[0]" = "1"
register "PcieRpMaxPayload[0]" = "RpMaxPayload_256"
@ -188,28 +188,28 @@ chip soc/intel/cannonlake
register "PcieRpAspm[0]" = "AspmDisabled"
end
device ref pcie_rp5 on # PHY 3
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
device pci 00.0 on
smbios_dev_info 3
end
end
device ref pcie_rp6 on # PHY 4
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieRpLtrEnable[5]" = "1"
device pci 00.0 on
smbios_dev_info 4
end
end
device ref pcie_rp7 on # PHY 2
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
device pci 00.0 on
smbios_dev_info 2
end
end
device ref pcie_rp8 on # PHY 1
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
device pci 00.0 on
smbios_dev_info 1
@ -217,12 +217,12 @@ chip soc/intel/cannonlake
end
device ref pcie_rp9 on
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpSlotImplemented[8]" = "1"
end
device ref pcie_rp14 on # PHY 0
register "PcieRpEnable[13]" = "1"
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
device pci 00.0 on
smbios_dev_info 0
@ -232,13 +232,13 @@ chip soc/intel/cannonlake
device pci 00.0 on # Aspeed PCI Bridge
device pci 00.0 on end # Aspeed 2500 VGA
end
register "PcieRpEnable[14]" = "1"
register "PcieRpEnable[14]" = "true"
register "PcieRpLtrEnable[14]" = "1"
register "PcieRpSlotImplemented[14]" = "1"
end
device ref pcie_rp16 on # M.2 E/CNVi
# Disabled when CNVi is present
register "PcieRpEnable[15]" = "1"
register "PcieRpEnable[15]" = "true"
register "PcieRpLtrEnable[15]" = "1"
register "PcieRpSlotImplemented[15]" = "1"
end

16
src/mainboard/protectli/vault_cml/devicetree.cb
View file

@ -52,14 +52,14 @@ chip soc/intel/cannonlake
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[2]" = "1"
register "PcieRpEnable[4]" = "1" # LAN1
register "PcieRpEnable[5]" = "1" # LAN2
register "PcieRpEnable[6]" = "1" # LAN3
register "PcieRpEnable[7]" = "1" # LAN4
register "PcieRpEnable[8]" = "1" # LAN5
register "PcieRpEnable[9]" = "1" # LAN6
register "PcieRpEnable[11]" = "1" # M.2 WiFi
register "PcieRpEnable[12]" = "1" # M.2 NVMe x4
register "PcieRpEnable[4]" = "true" # LAN1
register "PcieRpEnable[5]" = "true" # LAN2
register "PcieRpEnable[6]" = "true" # LAN3
register "PcieRpEnable[7]" = "true" # LAN4
register "PcieRpEnable[8]" = "true" # LAN5
register "PcieRpEnable[9]" = "true" # LAN6
register "PcieRpEnable[11]" = "true" # M.2 WiFi
register "PcieRpEnable[12]" = "true" # M.2 NVMe x4
# Enable Advanced Error Reporting for RP 5-10, 12, 13
register "PcieRpAdvancedErrorReporting[4]" = "1"

14
src/mainboard/protectli/vault_kbl/devicetree.cb
View file

@ -142,49 +142,49 @@ chip soc/intel/skylake
end
device ref pcie_rp1 on
# LAN
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpAdvancedErrorReporting[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpClkSrcNumber[0]" = "0"
end
device ref pcie_rp2 on
# LAN
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[1]" = "true"
register "PcieRpAdvancedErrorReporting[1]" = "1"
register "PcieRpLtrEnable[1]" = "1"
register "PcieRpClkSrcNumber[1]" = "1"
end
device ref pcie_rp3 on
# LAN
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[2]" = "true"
register "PcieRpAdvancedErrorReporting[2]" = "1"
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpClkSrcNumber[2]" = "2"
end
device ref pcie_rp4 on
# LAN
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[3]" = "true"
register "PcieRpAdvancedErrorReporting[3]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpClkSrcNumber[3]" = "3"
end
device ref pcie_rp5 on
# LAN
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpAdvancedErrorReporting[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpClkSrcNumber[4]" = "4"
end
device ref pcie_rp6 on
# LAN
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieRpAdvancedErrorReporting[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieRpClkSrcNumber[5]" = "5"
end
device ref pcie_rp9 on
# mPCIe WIFI
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpAdvancedErrorReporting[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpClkSrcNumber[8]" = "5"

8
src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
View file

@ -125,7 +125,7 @@ chip soc/intel/cannonlake
register "SataPortsDevSlp[2]" = "1"
end
device ref pcie_rp7 on # x1 M.2/E 2230 (WLAN)
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpSlotImplemented[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieRpHotPlug[6]" = "1"
@ -135,12 +135,12 @@ chip soc/intel/cannonlake
end
device ref pcie_rp8 on
device pci 00.0 on end # x1 (LAN)
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp9 on # x4 M.2/M 2280 (NVMe)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[0]" = "8"
@ -148,7 +148,7 @@ chip soc/intel/cannonlake
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpSlotImplemented[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[1]" = "12"

6
src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
View file

@ -118,7 +118,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp8 on # x1 M.2/E 2230 (WLAN)
register "PcieRpSlotImplemented[7]" = "1"
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
# ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC
register "PcieClkSrcUsage[2]" = "0x80"
@ -126,13 +126,13 @@ chip soc/intel/cannonlake
end
device ref pcie_rp10 on
device pci 00.0 on end # x1 (LAN)
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[9]" = "true"
register "PcieClkSrcUsage[3]" = "9"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
register "PcieRpSlotImplemented[12]" = "1"
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[1]" = "12"
register "PcieClkSrcClkReq[1]" = "1"

10
src/mainboard/purism/librem_l1um_v2/devicetree.cb
View file

@ -210,20 +210,20 @@ chip soc/intel/cannonlake
end
device ref pcie_rp21 on
register "PcieRpSlotImplemented[20]" = "1"
register "PcieRpEnable[20]" = "1"
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieClkSrcUsage[10]" = "20"
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X"
end
device ref pcie_rp1 on
register "PcieRpSlotImplemented[0]" = "1"
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpLtrEnable[0]" = "1"
register "PcieClkSrcUsage[1]" = "0x80"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X"
end
device ref pcie_rp9 on # GbE #1
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[14]" = "8"
# Type indexes are needed for systemd to use "onboard" names by default
@ -236,12 +236,12 @@ chip soc/intel/cannonlake
end
end
device ref pcie_rp10 on # BMC video
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[9]" = "true"
register "PcieRpLtrEnable[9]" = "1"
register "PcieClkSrcUsage[8]" = "9"
end
device ref pcie_rp11 on # GbE #2
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieClkSrcUsage[11]" = "10"
device pci 00.0 on

4
src/mainboard/purism/librem_skl/devicetree.cb
View file

@ -144,10 +144,10 @@ chip soc/intel/skylake
}"
end
device ref pcie_rp5 on
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
end
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
end
device ref lpc_espi on
# EC/KBC requires continuous mode

6
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
View file

@ -157,16 +157,16 @@ chip soc/intel/skylake
device ref uart2 on end
device ref pcie_rp1 on end
device ref pcie_rp3 on
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[2]" = "true"
register "PcieRpLtrEnable[2]" = "1"
end
device ref pcie_rp5 on
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
end
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
end
device ref lpc_espi on

8
src/mainboard/siemens/chili/variants/base/devicetree.cb
View file

@ -38,25 +38,25 @@ chip soc/intel/cannonlake
end
device ref pcie_rp5 on
device pci 00.0 on end # x1 i219
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieClkSrcUsage[4]" = "0x70"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieRpSlotImplemented[4]" = "0"
end
device ref pcie_rp6 on
device pci 00.0 on end # x1 i210
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieClkSrcUsage[5]" = "5"
register "PcieClkSrcClkReq[5]" = "5"
register "PcieRpSlotImplemented[5]" = "0"
end
device ref pcie_rp7 on
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpSlotImplemented[6]" = "1"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
end
device ref pcie_rp17 on
register "PcieRpEnable[16]" = "1"
register "PcieRpEnable[16]" = "true"
register "PcieClkSrcUsage[7]" = "16"
register "PcieClkSrcClkReq[7]" = "7"
register "PcieRpSlotImplemented[16]" = "1"

12
src/mainboard/siemens/chili/variants/chili/devicetree.cb
View file

@ -81,39 +81,39 @@ chip soc/intel/cannonlake
end
end
device ref pcie_rp1 off
register "PcieRpEnable[0]" = "0" # Debug (x1)
register "PcieRpEnable[0]" = "false" # Debug (x1)
register "PcieClkSrcUsage[2]" = "0"
register "PcieClkSrcClkReq[2]" = "2"
end
device ref pcie_rp5 on
register "PcieRpEnable[4]" = "1" # CORE (x1)
register "PcieRpEnable[4]" = "true" # CORE (x1)
register "PcieClkSrcUsage[4]" = "4"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieRpSlotImplemented[4]" = "1"
end
device ref pcie_rp6 on
device pci 00.0 on end # i210 (x1)
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieClkSrcUsage[5]" = "5"
register "PcieClkSrcClkReq[5]" = "5"
register "PcieRpSlotImplemented[5]" = "0"
end
device ref pcie_rp7 on
device pci 00.0 on end # VL805 Front Rack/UIB (x1)
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieClkSrcUsage[1]" = "6"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieRpSlotImplemented[6]" = "0"
end
device ref pcie_rp8 on
device pci 00.0 on end # VL805 Back MB (x1)
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieClkSrcUsage[0]" = "7"
register "PcieClkSrcClkReq[0]" = "0"
register "PcieRpSlotImplemented[7]" = "0"
end
device ref pcie_rp17 on
register "PcieRpEnable[16]" = "1" # NVMe (x4)
register "PcieRpEnable[16]" = "true" # NVMe (x4)
register "PcieClkSrcUsage[7]" = "16"
register "PcieClkSrcClkReq[7]" = "7"
register "PcieRpSlotImplemented[16]" = "1"

14
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb
View file

@ -49,34 +49,34 @@ chip soc/intel/skylake
end
device ref igpu on end
device ref pcie_rp1 on
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
device pci 00.0 on end # GbE
end
device ref pcie_rp2 on
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[1]" = "true"
device pci 00.0 on end # GbE
end
device ref pcie_rp3 on
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[2]" = "true"
device pci 00.0 on end # GbE
end
device ref pcie_rp4 on
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[3]" = "true"
device pci 00.0 on end # GbE
end
device ref pcie_rp5 on
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X"
end
device ref pcie_rp7 on
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
device pci 00.0 on # Aspeed PCI Bridge
device pci 00.0 on end # Aspeed 2400 VGA
end
end
device ref pcie_rp9 on
# Slot JPCIE1
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
end
device ref lpc_espi on

8
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
View file

@ -41,12 +41,12 @@ chip soc/intel/skylake
device ref peg0 on end # unused
device ref peg1 on
# Slot JPCIE1
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
end
device ref pcie_rp1 on
# Slot JPCIE1
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[2]" = "true"
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
end
device ref pcie_rp3 on
@ -55,12 +55,12 @@ chip soc/intel/skylake
end
end
device ref pcie_rp5 on
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
device pci 00.0 on end # 10GbE
device pci 00.1 on end # 10GbE
end
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
end
device ref lpc_espi on

10
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
View file

@ -44,20 +44,20 @@ chip soc/intel/skylake
end
device ref pcie_rp1 on
# Slot JPCIE4
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpAdvancedErrorReporting[0]" = "1"
smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
end
device ref pcie_rp5 on
# Slot JPCIE5
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpAdvancedErrorReporting[4]" = "1"
smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
end
device ref pcie_rp9 on
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpAdvancedErrorReporting[8]" = "1"
device pci 00.0 on # GbE 1
@ -65,7 +65,7 @@ chip soc/intel/skylake
end
end
device ref pcie_rp10 on
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[9]" = "true"
register "PcieRpLtrEnable[9]" = "1"
register "PcieRpAdvancedErrorReporting[9]" = "1"
device pci 00.0 on # GbE 2
@ -73,7 +73,7 @@ chip soc/intel/skylake
end
end
device ref pcie_rp11 on
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
register "PcieRpAdvancedErrorReporting[10]" = "1"
device pci 00.0 on # Aspeed PCI Bridge

10
src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb
View file

@ -45,24 +45,24 @@ chip soc/intel/skylake
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X"
end
device ref pcie_rp1 on
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
device pci 00.0 on end # GbE
end
device ref pcie_rp2 on
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[1]" = "true"
device pci 00.0 on end # GbE
end
device ref pcie_rp5 on
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
end
device ref pcie_rp9 on
# Slot JSXB2
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" "PCH SLOT2 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
end
device ref pcie_rp13 on
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
device pci 00.0 on # Aspeed PCI Bridge
device pci 00.0 on end # Aspeed 2400 VGA
end

12
src/mainboard/system76/addw1/devicetree.cb
View file

@ -98,7 +98,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp17 on
# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
register "PcieRpEnable[16]" = "1"
register "PcieRpEnable[16]" = "true"
register "PcieRpLtrEnable[16]" = "1"
register "PcieRpHotPlug[16]" = "1"
register "PcieClkSrcUsage[0]" = "16"
@ -106,7 +106,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp21 on
# PCI Express root port #21 x4, Clock 10 (SSD2)
register "PcieRpEnable[20]" = "1"
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieClkSrcUsage[10]" = "20"
register "PcieClkSrcClkReq[10]" = "10"
@ -114,7 +114,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp9 on
# PCI Express root port #9 x4, Clock 9 (SSD1)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[9]" = "8"
register "PcieClkSrcClkReq[9]" = "9"
@ -122,7 +122,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp14 on
# PCI Express root port #14 x1, Clock 5 (GLAN)
register "PcieRpEnable[13]" = "1"
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieClkSrcUsage[5]" = "13"
register "PcieClkSrcClkReq[5]" = "5"
@ -130,7 +130,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp15 on
# PCI Express root port #15 x1, Clock 7 (Card Reader)
register "PcieRpEnable[14]" = "1"
register "PcieRpEnable[14]" = "true"
register "PcieRpLtrEnable[14]" = "1"
register "PcieClkSrcUsage[7]" = "14"
register "PcieClkSrcClkReq[7]" = "7"
@ -138,7 +138,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp16 on
# PCI Express root port #16 x1, Clock 6 (WLAN)
register "PcieRpEnable[15]" = "1"
register "PcieRpEnable[15]" = "true"
register "PcieRpLtrEnable[15]" = "1"
register "PcieClkSrcUsage[6]" = "15"
register "PcieClkSrcClkReq[6]" = "6"

16
src/mainboard/system76/bonw14/devicetree.cb
View file

@ -113,21 +113,21 @@ chip soc/intel/cannonlake
end
device ref pcie_rp17 on
# PCI Express root port #17 x4, Clock 14 (SSD2)
register "PcieRpEnable[16]" = "1"
register "PcieRpEnable[16]" = "true"
register "PcieRpLtrEnable[16]" = "1"
register "PcieClkSrcUsage[14]" = "16"
register "PcieClkSrcClkReq[14]" = "14"
end
device ref pcie_rp21 on
# PCI Express root port #21 x4, Clock 15 (SSD3)
register "PcieRpEnable[20]" = "1"
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieClkSrcUsage[15]" = "20"
register "PcieClkSrcClkReq[15]" = "15"
end
device ref pcie_rp1 on
# PCI Express root port #1 x4, Clock 6 (Thunderbolt)
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpHotPlug[0]" = "1"
register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED
@ -135,35 +135,35 @@ chip soc/intel/cannonlake
end
device ref pcie_rp5 on
# PCI Express root port #5 x4, Clock 10 (USB 3.2)
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieClkSrcUsage[10]" = "4"
register "PcieClkSrcClkReq[10]" = "10"
end
device ref pcie_rp9 on
# PCI Express root port #9 x4, Clock 8 (SSD)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[8]" = "8"
register "PcieClkSrcClkReq[8]" = "8"
end
device ref pcie_rp13 on
# PCI Express root port #13 x1, Clock 0 (WLAN)
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[0]" = "12"
register "PcieClkSrcClkReq[0]" = "0"
end
device ref pcie_rp14 on
# PCI Express root port #14 x1, Clock 1 (GLAN)
register "PcieRpEnable[13]" = "1"
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieClkSrcUsage[1]" = "13"
register "PcieClkSrcClkReq[1]" = "1"
end
device ref pcie_rp15 on
# PCI Express root port #15 x1, Clock 4 (Card Reader)
register "PcieRpEnable[14]" = "1"
register "PcieRpEnable[14]" = "true"
register "PcieRpLtrEnable[14]" = "1"
register "PcieClkSrcUsage[4]" = "14"
register "PcieClkSrcClkReq[4]" = "4"

8
src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
View file

@ -40,7 +40,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp5 on
# PCI Express Root port #5 x4, Clock 4 (TBT)
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[4]" = "4"
@ -48,21 +48,21 @@ chip soc/intel/cannonlake
end
device ref pcie_rp9 on
# PCI Express Root port #9 x1, Clock 3 (LAN)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 on
# PCI Express Root port #10 x1, Clock 2 (WLAN)
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[9]" = "true"
register "PcieRpLtrEnable[9]" = "0"
register "PcieClkSrcUsage[2]" = "9"
register "PcieClkSrcClkReq[2]" = "2"
end
device ref pcie_rp13 on
# PCI Express Root port #13 x4, Clock 5 (NVMe)
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"

8
src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
View file

@ -33,7 +33,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp5 on
# PCI Express Root port #5 x4, Clock 4 (TBT)
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[4]" = "4"
@ -41,21 +41,21 @@ chip soc/intel/cannonlake
end
device ref pcie_rp9 on
# PCI Express Root port #9 x1, Clock 3 (LAN)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 on
# PCI Express Root port #10 x1, Clock 2 (WLAN)
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[9]" = "true"
register "PcieRpLtrEnable[9]" = "0"
register "PcieClkSrcUsage[2]" = "9"
register "PcieClkSrcClkReq[2]" = "2"
end
device ref pcie_rp13 on
# PCI Express Root port #13 x4, Clock 5 (NVMe)
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"

8
src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
View file

@ -41,7 +41,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp6 on
device pci 00.0 on end # x1 Card reader
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieRpLtrEnable[5]" = "1"
register "PcieClkSrcUsage[3]" = "5"
register "PcieClkSrcClkReq[3]" = "3"
@ -49,7 +49,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp8 on
device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
register "PcieRpEnable[7]" = "1"
register "PcieRpEnable[7]" = "true"
register "PcieRpLtrEnable[7]" = "1"
register "PcieClkSrcUsage[2]" = "7"
register "PcieClkSrcClkReq[2]" = "2"
@ -61,7 +61,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp9 on
device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[4]" = "8"
register "PcieClkSrcClkReq[4]" = "4"
@ -70,7 +70,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp13 on
device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"

8
src/mainboard/system76/gaze15/devicetree.cb
View file

@ -96,7 +96,7 @@ chip soc/intel/cannonlake
device ref uart2 on end
device ref pcie_rp21 on
# PCI Express root port #21 x4, Clock 11 (SSD2)
register "PcieRpEnable[20]" = "1"
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieClkSrcUsage[11]" = "20"
register "PcieClkSrcClkReq[11]" = "11"
@ -104,7 +104,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp9 on
# PCI Express root port #9 x4, Clock 10 (SSD)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[10]" = "8"
register "PcieClkSrcClkReq[10]" = "10"
@ -112,7 +112,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp14 on
# PCI Express root port #14 x1, Clock 6 (WLAN)
register "PcieRpEnable[13]" = "1"
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieClkSrcUsage[6]" = "13"
register "PcieClkSrcClkReq[6]" = "6"
@ -120,7 +120,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp15 on
# PCI Express root port #15 x1, Clock 5 (LAN)
register "PcieRpEnable[14]" = "1"
register "PcieRpEnable[14]" = "true"
register "PcieRpLtrEnable[14]" = "1"
register "PcieClkSrcUsage[5]" = "14"
register "PcieClkSrcClkReq[5]" = "5"

8
src/mainboard/system76/kbl-u/devicetree.cb
View file

@ -133,7 +133,7 @@ chip soc/intel/skylake
end
device ref pcie_rp1 on
# Root port #1 x4 (TBT)
register "PcieRpEnable[0]" = "1"
register "PcieRpEnable[0]" = "true"
register "PcieRpClkReqSupport[0]" = "1"
register "PcieRpClkReqNumber[0]" = "4"
register "PcieRpClkSrcNumber[0]" = "4"
@ -143,7 +143,7 @@ chip soc/intel/skylake
end
device ref pcie_rp5 on
# Root port #5 x1 (LAN)
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpClkReqSupport[4]" = "1"
register "PcieRpClkReqNumber[4]" = "3"
register "PcieRpClkSrcNumber[4]" = "3"
@ -152,7 +152,7 @@ chip soc/intel/skylake
end
device ref pcie_rp6 on
# Root port #6 x1 (WLAN)
register "PcieRpEnable[5]" = "1"
register "PcieRpEnable[5]" = "true"
register "PcieRpClkReqSupport[5]" = "1"
register "PcieRpClkReqNumber[5]" = "2"
register "PcieRpClkSrcNumber[5]" = "2"
@ -161,7 +161,7 @@ chip soc/intel/skylake
end
device ref pcie_rp9 on
# Root port #9 x4 (NVMe)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpClkReqSupport[8]" = "1"
register "PcieRpClkReqNumber[8]" = "5"
register "PcieRpClkSrcNumber[8]" = "5"

10
src/mainboard/system76/oryp5/devicetree.cb
View file

@ -109,35 +109,35 @@ chip soc/intel/cannonlake
device ref uart2 on end
device ref pcie_rp21 on
# PCI Express root port #21 x4, Clock 11 (SSD2)
register "PcieRpEnable[20]" = "1"
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieClkSrcUsage[11]" = "20"
register "PcieClkSrcClkReq[11]" = "11"
end
device ref pcie_rp9 on
# PCI Express root port #9 x4, Clock 12 (SSD)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[12]" = "8"
register "PcieClkSrcClkReq[12]" = "12"
end
device ref pcie_rp14 on
# PCI Express root port #14 x1, Clock 13 (WLAN)
register "PcieRpEnable[13]" = "1"
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieClkSrcUsage[13]" = "13"
register "PcieClkSrcClkReq[13]" = "13"
end
device ref pcie_rp15 on
# PCI Express root port #15 x1, Clock 14 (GLAN)
register "PcieRpEnable[14]" = "1"
register "PcieRpEnable[14]" = "true"
register "PcieRpLtrEnable[14]" = "1"
register "PcieClkSrcUsage[14]" = "14"
register "PcieClkSrcClkReq[14]" = "14"
end
device ref pcie_rp16 on
# PCI Express root port #16 x1, Clock 15 (Card Reader)
register "PcieRpEnable[15]" = "1"
register "PcieRpEnable[15]" = "true"
register "PcieRpLtrEnable[15]" = "1"
register "PcieClkSrcUsage[15]" = "15"
register "PcieClkSrcClkReq[15]" = "15"

12
src/mainboard/system76/oryp6/devicetree.cb
View file

@ -106,7 +106,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp17 on
# PCI Express root port #17 x4, Clock 0 (Thunderbolt)
register "PcieRpEnable[16]" = "1"
register "PcieRpEnable[16]" = "true"
register "PcieRpLtrEnable[16]" = "1"
register "PcieRpHotPlug[16]" = "1"
register "PcieClkSrcUsage[0]" = "16"
@ -115,7 +115,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp21 on
# PCI Express root port #21 x4, Clock 11 (SSD2)
register "PcieRpEnable[20]" = "1"
register "PcieRpEnable[20]" = "true"
register "PcieRpLtrEnable[20]" = "1"
register "PcieClkSrcUsage[11]" = "20"
register "PcieClkSrcClkReq[11]" = "11"
@ -123,7 +123,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp9 on
# PCI Express root port #9 x4, Clock 12 (SSD1)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[12]" = "8"
register "PcieClkSrcClkReq[12]" = "12"
@ -131,7 +131,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp14 on
# PCI Express root port #14 x1, Clock 7 (GLAN)
register "PcieRpEnable[13]" = "1"
register "PcieRpEnable[13]" = "true"
register "PcieRpLtrEnable[13]" = "1"
register "PcieClkSrcUsage[7]" = "13"
register "PcieClkSrcClkReq[7]" = "7"
@ -139,7 +139,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp15 on
# PCI Express root port #15 x1, Clock 9 (Card Reader)
register "PcieRpEnable[14]" = "1"
register "PcieRpEnable[14]" = "true"
register "PcieRpLtrEnable[14]" = "1"
register "PcieClkSrcUsage[9]" = "14"
register "PcieClkSrcClkReq[9]" = "9"
@ -147,7 +147,7 @@ chip soc/intel/cannonlake
end
device ref pcie_rp16 on
# PCI Express root port #16 x1, Clock 6 (WLAN)
register "PcieRpEnable[15]" = "1"
register "PcieRpEnable[15]" = "true"
register "PcieRpLtrEnable[15]" = "1"
register "PcieClkSrcUsage[6]" = "15"
register "PcieClkSrcClkReq[6]" = "6"

8
src/mainboard/system76/whl-u/devicetree.cb
View file

@ -99,7 +99,7 @@ chip soc/intel/cannonlake
device ref pcie_rp1 on end
device ref pcie_rp5 on
# PCI Express Root port #5 x4, Clock 4 (TBT)
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[4]" = "true"
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[4]" = "4"
@ -107,21 +107,21 @@ chip soc/intel/cannonlake
end
device ref pcie_rp9 on
# PCI Express Root port #9 x1, Clock 3 (LAN)
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 on
# PCI Express Root port #10 x1, Clock 2 (WLAN)
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[9]" = "true"
register "PcieRpLtrEnable[9]" = "0"
register "PcieClkSrcUsage[2]" = "9"
register "PcieClkSrcClkReq[2]" = "2"
end
device ref pcie_rp13 on
# PCI Express Root port #13 x4, Clock 5 (NVMe)
register "PcieRpEnable[12]" = "1"
register "PcieRpEnable[12]" = "true"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"

4
util/mainboard/google/puff/template/overridetree.cb
View file

@ -183,10 +183,10 @@ chip soc/intel/cannonlake
}"
# PCIe port 7 for LAN
register "PcieRpEnable[6]" = "1"
register "PcieRpEnable[6]" = "true"
register "PcieRpLtrEnable[6]" = "1"
# PCIe port 11 (x2) for NVMe hybrid storage devices
register "PcieRpEnable[10]" = "1"
register "PcieRpEnable[10]" = "true"
register "PcieRpLtrEnable[10]" = "1"
# Uses CLK SRC 0
register "PcieClkSrcUsage[0]" = "6"