mb/starlabs/*: Correct config for SATA DEVSLP GPIO

On boards that do not use SATA, this should be connected.

For boards that do use it, it should be NF5.

Change-Id: I3115627431e80bd5e0f91b53b80fac7c0c95e6f8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86186
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2025-01-28 14:07:05 +00:00
commit 582f7c4374
4 changed files with 4 additions and 3 deletions

View file

@ -362,7 +362,7 @@ const struct pad_config gpio_table[] = {
/* H12: Not Connected */
PAD_NC(GPP_H12, NONE),
/* H13: PCH M.2 SSD Device Sleep */
PAD_CFG_GPO(GPP_H13, 0, PLTRST),
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
/* H14: Not Connected */
PAD_NC(GPP_H14, NONE),
/* H15: DDPB Control Clock */

View file

@ -361,7 +361,7 @@ const struct pad_config gpio_table[] = {
/* H12: Not Connected */
PAD_NC(GPP_H12, NONE),
/* H13: PCH M.2 SSD Device Sleep */
PAD_CFG_GPO(GPP_H13, 0, PLTRST),
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
/* H14: Not Connected */
PAD_NC(GPP_H14, NONE),
/* H15: DDPB Control Clock */

View file

@ -202,6 +202,7 @@ const struct pad_config gpio_table[] = {
/* E03: */
PAD_NC(GPP_E03, NONE),
/* E04: M.2_SSD_DEVSLP0 */
PAD_NC(GPP_E04, NONE),
/* E05: */
PAD_NC(GPP_E05, NONE),
/* E06: JTAG ODT

View file

@ -358,7 +358,7 @@ const struct pad_config gpio_table[] = {
/* H12: Not Connected */
PAD_NC(GPP_H12, NONE),
/* H13: PCH M.2 SSD Device Sleep */
PAD_CFG_GPO(GPP_H13, 0, PLTRST),
PAD_NC(GPP_H13, NONE),
/* H14: Not Connected */
PAD_NC(GPP_H14, NONE),
/* H15: DDPB Control Clock */