mb/starlabs/*: Correct config for SATA DEVSLP GPIO
On boards that do not use SATA, this should be connected. For boards that do use it, it should be NF5. Change-Id: I3115627431e80bd5e0f91b53b80fac7c0c95e6f8 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86186 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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4 changed files with 4 additions and 3 deletions
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@ -362,7 +362,7 @@ const struct pad_config gpio_table[] = {
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/* H12: Not Connected */
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PAD_NC(GPP_H12, NONE),
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/* H13: PCH M.2 SSD Device Sleep */
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PAD_CFG_GPO(GPP_H13, 0, PLTRST),
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PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
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/* H14: Not Connected */
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PAD_NC(GPP_H14, NONE),
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/* H15: DDPB Control Clock */
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@ -361,7 +361,7 @@ const struct pad_config gpio_table[] = {
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/* H12: Not Connected */
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PAD_NC(GPP_H12, NONE),
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/* H13: PCH M.2 SSD Device Sleep */
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PAD_CFG_GPO(GPP_H13, 0, PLTRST),
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PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
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/* H14: Not Connected */
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PAD_NC(GPP_H14, NONE),
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/* H15: DDPB Control Clock */
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@ -202,6 +202,7 @@ const struct pad_config gpio_table[] = {
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/* E03: */
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PAD_NC(GPP_E03, NONE),
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/* E04: M.2_SSD_DEVSLP0 */
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PAD_NC(GPP_E04, NONE),
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/* E05: */
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PAD_NC(GPP_E05, NONE),
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/* E06: JTAG ODT
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@ -358,7 +358,7 @@ const struct pad_config gpio_table[] = {
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/* H12: Not Connected */
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PAD_NC(GPP_H12, NONE),
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/* H13: PCH M.2 SSD Device Sleep */
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PAD_CFG_GPO(GPP_H13, 0, PLTRST),
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PAD_NC(GPP_H13, NONE),
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/* H14: Not Connected */
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PAD_NC(GPP_H14, NONE),
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/* H15: DDPB Control Clock */
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