mb/starlabs/*: Explicitly set Early Command Training

Explicitly set ECT in romstage; enable it for boards that use
LPxxx memory and disable it for boards that use SODIMMs.

Change-Id: I41bd9b221dc97bb4f76862f7095c20f4b8bc6036
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes 2025-01-29 12:27:46 +00:00
commit 10cf6658f7
7 changed files with 7 additions and 1 deletions

View file

@ -9,6 +9,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg mem_config = {
.type = MEM_TYPE_DDR4,
.ect = false,
.UserBd = BOARD_TYPE_ULT_ULX,
};

View file

@ -9,6 +9,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg mem_config = {
.type = MEM_TYPE_DDR4,
.ect = false,
.UserBd = BOARD_TYPE_MOBILE,
};

View file

@ -9,6 +9,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg mem_config = {
.type = MEM_TYPE_DDR4,
.ect = false,
.UserBd = BOARD_TYPE_ULT_ULX,
};

View file

@ -66,7 +66,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
.rcomp_targets = {100, 40, 20, 20, 26},
.dq_pins_interleaved = 0,
.vref_ca_config = 2,
.ect = 0,
.ect = true,
};
const uint8_t vtd = get_uint_option("vtd", 1);

View file

@ -9,6 +9,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg mem_config = {
.type = MEM_TYPE_DDR5,
.ect = false,
.UserBd = BOARD_TYPE_MOBILE,
};

View file

@ -9,6 +9,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg mem_config = {
.type = MEM_TYPE_DDR4,
.ect = false,
.UserBd = BOARD_TYPE_MOBILE,
};

View file

@ -9,6 +9,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const struct mb_cfg mem_config = {
.type = MEM_TYPE_DDR4,
.ect = false,
};
const bool half_populated = false;