According to the latest SPD parameters provided by the manufacturer,
combined with the document 8Gb_LPDDR4X_B_Die_component_Datasheet(S).pdf
we correct channelsPerDie, diesPerPackage, ranksPerChannel of SPD
for Nanya NT6AP1024F32BL-J1; merged the parameters into the BIOS and
flashed it into the machine. The machine can boot and read the normal
size of memory.
BUG=b.422906387
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
Use the dmidecode -t memory command to read the size of memory.
Output results：
awasuki-rev2 # dmidecode -t memory
# dmidecode 3.4
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x000A, DMI type 16, 23 bytes
Physical Memory Array
Location: System Board Or Motherboard
Use: System Memory
Error Correction Type: None
Maximum Capacity: 64 GB
Error Information Handle: Not Provided
Number Of Devices: 4
Handle 0x000B, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 32 bits
Data Width: 32 bits
Size: 8 GB
Form Factor: Unknown
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: LPDDR4
Type Detail: Synchronous
Speed: 2933 MT/s
Manufacturer: Unknown (b03)
Serial Number: 00000000
Asset Tag: Not Specified
Part Number: NT6AP1024F32BL-J1
Rank: 2
Configured Memory Speed: 2933 MT/s
Minimum Voltage: 0.6 V
Maximum Voltage: 0.6 V
Configured Voltage: 0.6 V
Change-Id: I35823ce87b5d8d67894528e4a8781dd91247eb6c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88146
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current approach has two problems:
- Just because the source address is 0 does not mean it is no
specifically set. A bunch of mainboards specify their APOB_NV base
address at 0 in their FMAP files.
- There is no AMD SOC that has support for this binary, but doesn't give
AMDFWTOOL the base address. It would also not work considering that
AMD common/block/apob code gets the region from the FMAP.
Therefore just remove the check since no mainboard will ever enter the
else branch.
tested: binary identical for at least 1 mainboard on each SOC
generation.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic85d6b25c95ab12dbcc72d17158591891dd04e97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add ACPI ASL code for the discrete NVIDIA GN21 GPU. Based on
google/brya, but adapted for Meteor Lake and the specific GPU found in
Clevo V5x0TNx.
NVIDIA did not provide us with the required documentation, so this
driver is entirely based on the Brya implementation, and poking Clevo
ACPI from Linux.
Without this patch, the NVIDIA driver would not load at all under
Windows, while Ubuntu would load the driver, but would be unable to
power off the dGPU, causing increased power draw.
TEST=Boot to Windows 11 via MrChromebox uefipayload_2502 and observe
that the NVIDIA Driver loads correctly, that the dGPU powers off when
unused and powers on while needed. Do the same in Ubuntu 24.04 under a
Gnome X11 session.
Change-Id: I9e5715cb4129a005cc9374fd53eaacd7d1a7f68e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
This partially reverts commit 32ebaef73c
("mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE")
as google/brox board has moved away from the PAD_CFG_GPI_INT_SWAPPED
usage. The revert simply removes the PAD_CFG_GPI_INT_SWAPPED solution,
which is not used anywhere anymore.
PAD_CFG0_ROUTE_SWAPPED bit can not be found in any PCH datasheet nor
EDS. Furthermore, the definition conflicts with PAD_CFG0_NAFVWE_ENABLE
bit, which, on the contrary, is defined in the datasheets and PCH EDS.
The conflict results in boards printing:
"GPIO XX doesn't support APIC routing," (where XX is pad number)
for each pad having the NAFVWE bit set.
Currently, none of the boards use PAD_CFG0_ROUTE_SWAPPED bit, and due
to the bit field conflict I assume it was mistakenly added.
Change-Id: I71299c9729f294cfafaec02222ef01e96b575740
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87485
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Due to layout restrictions on mc_ehl3, the eMMC interface is limited to
operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not
supported. Limit the capabilities in the eMMC controller to DDR50 mode
only so that the eMMC driver in OS will choose the right mode for
operation even if the attached eMMC card supports higher modes.
BUG=none
TEST=Boot into Linux and check dmesg output for mmc modes
Change-Id: Id84d34e7abd4bf73648d453182345bc2e4676d62
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88110
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Set slow_slew_rate for VCCIA and VCCGT to SLEW_FAST_8 to improve EE
noise for meliks.
BRANCH=nissa
TEST=built firmware and got pass for EE noise test.
Change-Id: Ie1a9147736e3effa465134854ecd34554bee6906
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88126
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Doan <edoan@chromium.org>
This commit eliminates the power limit constraints initially adopted
from the Fatcat board's codebase. These constraints are tailored for
factory-specific scenarios, which are irrelevant to the Intel Panther
Lake RVP (PTLRVP) board's use case.
Change-Id: I3e4dfe85a2677ad3998fd6c0f9a59fa966587c59
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88132
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit addresses an issue within the DMAR (DMA Remapping) table
configuration for Intel Panther Lake (PTL) SoC. Specifically, it
introduces telemetry support to the DRHC structure. In addition, the
unnecessary Dynamic Platform and Thermal Framework (DPTF) entry is
removed from the SATC structure, aligning with the BIOS Requirements.
For detailed specifications, refer to the 812562 PTL Firmware
Architecture Specification (FAS).
BUG=b:423943431
TEST=Boot Fatcat board to ALOS. Disassemble the DMAR table using 2023+
version of iasl and check the DMAR for the telemetry entry in the DRHC
structure. There should not be a DPTF entry in the SATC structure.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I289f2520e4449a6aa33f53040b6c8f66faa4f2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88136
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A need arose to perform power and performance analysis on various SoC
SKUs with Fast VMode enabled, which the current chipset data structure
does not allow.
This commit refactors the configuration of Fast VMode I_TRIP thresholds
for Voltage Regulator (VR) domains across different power limit
configurations in Pantherlake SoCs. Previously, the I_TRIP threshold
values were statically set for each VR domain, but now they are defined
within a two-dimensional array that considers various power limit
scenarios.
This commit adds the I_TRIP values for different Power Limit SKUs
currently operated on Fatcat devices.
As part of this commit, the following two changes are being undone
because the previous code structure is now incompatible and lacks
purpose:
- commit 4b765fdd98 ("mb/google/fatcat: Disable EnableFastVmode on
Panther Lake H SoC")
- commit 5d7e2b4c0c ("mb/google/fatcat: Disable VR settings on Panther
Lake H SoC")
Change-Id: Iff21a9b0b230e08b99e032400cbe0021b8a4af43
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces support for additional Intel Panther Lake CPU IDs
in the `power_optimized_limits` structure, enhancing compatibility with
newer hardware. It also introduces macros for common power limit values,
streamlining the code and reducing repetition.
Change-Id: I6d7c24441ce6ed78c366f18627c237a2f4984cd5
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88131
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds the relevant IDs to support new Panther Lake (PTL)
System on Chips (SoCs). The CPU profiles are aligned with the matching
definition from Panther Lake Firmware Support Package (FSP) revision
3144.01.
TEST=A Fatcat device with CPUID 0xc06c1 and MCH_ID 0xb003 booted with
the relevant information printed in corebot logs.
[DEBUG] CPU: ID c06c1, Pantherlake B0, ucode: 00000105
[DEBUG] MCH: device id b003 (rev 06) is Pantherlake U
[DEBUG] PCH: device id e401 (rev 01) is Pantherlake SOC-H SuperSKU
[DEBUG] IGD: device id b090 (rev 00) is Pantherlake-U GT2
Change-Id: I66efe51a94edfffc2546817d06a63a9c4b51aa81
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88130
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit introduces the configuration and enabling of Thermal Design
Current (TDC) settings for various Panther Lake (PTL) SKUs. TDC values
are essential for managing thermal constraints, specifying the maximum
allowable current for specific Voltage Regulator (VR) domains under
given power limit scenarios. This enhancement provides tailored power
management for different SKUs, extracted from the Power Map Document
(#813278) which the Firmware Support Package (FSP) is not aligned with.
It introduces a new enum `soc_intel_pantherlake_sku` to represent
various SKUs as the current `soc_intel_pantherlake_power_limits` does
not meet the need for TDC settings. `cpuid_to_ptl` is updated to include
SKU mapping.
The VR romstage FSP params function implements logic to read SKU
information based on PCI device ID and CPU TDP, ensuring accurate
configuration.
TEST=FSP logs confirm TDC enablement at the specified values on a Fatcat
device operating an H12Xe Panther Lake SoC.
Change-Id: I889d5f08b0c75b950e5a30d25d6a370cccd295aa
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88039
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit makes power limit helper functions accessible during
romstage by updating the Makefile to include `power_limit.c` for both
ramstage and romstage.
It also modifies a preprocessor directive to ensure
`variant_update_cpu_power_limits()` is not compiled in romstage as it is
only intended for late-in-the-boot usage and will not compile properly
in romstage.
This change enables power management configuration identification early
in the boot process, allowing for better control over power settings at
this stage.
TEST=Successfully compile the Fatcat board target.
Change-Id: Ibf4d85c71dd8963063ca014d151438b68ea918db
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88038
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit exposes the Thermal Design Current (TDC) limit in the
FSP_M_CONFIG structure. The TDC Current Limit is defined in 1/8A
increments. This allows for more precise control over the thermal design
current settings, enhancing power management capabilities.
Change-Id: Ie35611d5cdc14114542ac1a61611aa333c4bb1c9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
The previous default value of 10 milliseconds is being updated to 50
milliseconds to comply with the latest guidelines (Panther Lake FSP
release 3144.01 CnviWifi.asl file).
TEST=Invoke the following set of acpidbg commands to verify that the
_RST method still reaches state 2.
acpidbg -b 'evaluate \_SB.PCI0.CNVW.PRRS' # 0x0
acpidbg -b 'set N \_SB.PCI0.CNVW.RSTT 1'
acpidbg -b 'evaluate \_SB.PCI0.CNVW.CNVP._RST'
acpidbg -b 'evaluate \_SB.PCI0.CNVW.PRRS' # 0x2
Change-Id: I2b0236c17117d368c1ee98e56c4c1b6525d63e27
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Introduce a new ACPI field, "WFDL", to specify the Power Level Device
Reset (PLDR) delay for Wi-Fi operations. This replaces the previously
hardcoded delay value, allowing for easier adjustment and configuration
of the PLDR timing in the future. By utilizing a named field, this
change facilitates potential updates to delay configurations.
Change-Id: I0f243ccf404afb83554136a3a310a98d6100d8ff
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Align the ACPI code comments with the actual generated code for Wi-Fi
power resource management. This change enhances the maintainability and
readability of the code by ensuring that comments accurately reflect the
runtime SSDT code.
Change-Id: Ie33c716305251356a462b086fa8c61ec8d16c3cb
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88112
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The change introduces new Advanced Configuration and Power Interface
(ACPI) methods to handle Bluetooth device states, including status
checks and device reset procedures. Specifically, it adds a Power
Resource for Reset (_PRR) method and the associated power resources to
enable Operating System (OS)-level resets for Connectivity Integrated
(CNVi) Bluetooth devices as specified in Intel document
number 559910. This allows the OS to perform Bluetooth hardware recovery
in case of errors, ensuring compliance with Intel's standards. The Power
Resource ACPI code was adapted from Panther Lake (PTL) Firmware Support
Package (FSP) revision 3144.01.
The new ACPI Bluetooth code introduces the CNMT mutex, similar to the
USB Bluetooth ACPI code, to avoid simultaneous CNVi resets when
executing Wi-Fi and Bluetooth power resource _RST methods.
TEST=The following two use cases were verified using acpidbg on a Fatcat
device.
1. Test CNVi Bluetooth _RST() completion.
acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x0
acpidbg -b 'evaluate \_SB.PCI0.CNVB.RSTT' # 0x0
acpidbg -b 'set N \_SB.PCI0.CNVB.RSTT 1' # 0x1
acpidbg -b 'evaluate \_SB.PCI0.CNVB.CNVP._RST'
acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x2
2. Test that CNVi Wi-Fi _RST calls CNVi Bluetooth CFLR method.
acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x0
acpidbg -b 'evaluate \_SB.PCI0.CNVW.RSTT' # 0x0
acpidbg -b 'set N \_SB.PCI0.CNVW.RSTT 1' # 0x0
acpidbg -b 'evaluate \_SB.PCI0.CNVW.CNVP._RST'
acpidbg -b 'evaluate \_SB.PCI0.CNVB.PRRS' # 0x1
Change-Id: I2389901faf4fad131bb7226e356b47f4b1a4ddac
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
DRAM Part Name ID to assign
H58G66CK8BX147 1 (0001)
Yavilla use three memory strap pins for RAM_ID definition and it's consumed.
Since the MT62F1G32D4DR-031 WT:B was never used so it's safe to remove.
This CL make the H58G66CK8BX147 to set for RAM_ID1.
BUG=b:425545256
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I9df2710ceb77e4ace6de8976adc1285ef9784c03
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88121
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Qualcomm's latest SoC, the x1p42100, lacks upstreamed blobs. This
prevents coreboot builds because the default setting marks
CONFIG_USE_QC_BLOBS=y. As a result, build errors occur when the new
Qualcomm SoC blobs aren't in the upstream.
This change introduces `QC_BLOBS_UPSTREAM` Kconfig and set to default
`N` to build QC platform without relying on upstream blob support.
This is necessary for bringing up a new QC SoC-based platform, as
public QC blobs won't be available until later in the year. This
ensures that early QC development can proceed for QC SoC based
without depending on upstream blobs.
Override this Kconfig when QC blobs are available in upstream for
latest X1P42100 SoC.
TEST=Able to build google/bluey.
Change-Id: I04fde6e8917fb3f88c58eb2b55b47de1c2d33518
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors the `soc_load_logo_by_coreboot()` function by
extracting common logo rendering logic into a new helper function:
`render_logo_to_framebuffer()`.
The `render_logo_to_framebuffer()` helper is responsible for:
- Loading the BMP image (by type).
- Checking the image size.
- Converting the BMP to GOP BLT format.
- Calculating the appropriate logo coordinates based on vertical
or horizontal alignment, considering panel orientation for the
footer logo.
- Copying the logo data to the framebuffer.
- Releasing the allocated logo buffer.
This refactoring significantly reduces code duplication within
`soc_load_logo_by_coreboot()`, making it more concise and readable.
It also centralizes the logo rendering process, improving
maintainability and simplifying future modifications.
The `soc_load_logo_by_coreboot()` function now focuses on
higher-level orchestration: graphics info initialization, MTRR
setup, panel orientation adjustment, and sequential calls to
`render_logo_to_framebuffer()` for the main and optional footer logos.
Error handling for MTRR and logo rendering failures is streamlined
with a `cleanup` goto label.
BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat at center of the
screen.
Change-Id: I10f84fd1c2081efcf787d00ab7cfc6bb24feca21
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88032
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When a ChromeOS device has `SPLASH_SCREEN_FOOTER` Kconfig enabled and
provides a logo path for an OEM-defined boot splash logo in the footer,
it indicates that the device doesn't need to render
`cb_plus_logo.bmp` logo (hence, avoid packing this bitmap for platforms
that select `SPLASH_SCREEN_FOOTER` Kconfig).
In such cases, only the main OEM logo should be displayed at the center
of the splash screen along with custom bitmap at footer of the splash
screen.
BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat.
Change-Id: Ie5085babe2f8373058ce1aa18b7071260f2aef7f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88099
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the explicit `logo_valignment` setting from the
`common_soc_config` for all Fatcat mainboard variants (fatcat, felino,
francka, and kinmen).
The default vertical alignment for the splash screen logo is
`FW_SPLASH_VALIGNMENT_CENTER`, which is the desired behavior for these
boards (in presence of footer logo).
BUG=b:423591644
TEST=Able to show OEM splash screen on google/fatcat at center of the
screen.
Change-Id: I3a9e86a928cdd76f13157eff2a29f209167613a8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit adds horizontal alignment support for splash screen
logos into the existing helper function `calculate_logo_coordinates()`.
Updated helper function determines the X-coordinate for
logo placement based on specified horizontal alignment (left, right,
or center).
The `soc_load_logo_by_coreboot()` function is updated to utilize this
helper for footer logo placement when the panel orientation is
rotated (`LB_FB_ORIENTATION_RIGHT_UP`, `LB_FB_ORIENTATION_LEFT_UP`,
or `LB_FB_ORIENTATION_BOTTOM_UP`).
A new enum, `fw_splash_horizontal_alignment`, is defined in
`intelblocks/cfg.h` to explicitly represent these horizontal alignment
options, complete with descriptive comments and ASCII art.
This enhancement provides greater flexibility in positioning splash
screen elements, especially useful for rotated displays (for the footer
firmware splash screen).
BUG=b:423591644
TEST=Able to rotate the firmware splash screen (including footer logo)
while using portrait panel.
Change-Id: I23ae6d06e1df9cad1b2907a5c02b619dc831d468
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88030
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refines the comments for the fw_splash_vertical_alignment
enum members in src/soc/intel/common/block/include/intelblocks/cfg.h.
The redundant enum member names (e.g., FW_SPLASH_VALIGNMENT_CENTER:)
have been removed from the start of each comment block. This makes
the comments cleaner and more direct, focusing on the explanation of
the alignment behavior rather than re-stating the enum member's name.
Change-Id: Ife7a39622df1981adc09db82fecb5adc72d52d8d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch modifies the low-battery shutdown logic to bail out early
when the system is in a low-power state. This prevents the display of
the OEM footer logo, ensuring power conservation and avoiding
unnecessary rendering alongside the low-battery icon.
BUG=b:423591644
TEST=Boot platform with `CONFIG(USE_COREBOOT_FOR_BMP_RENDERING)`
and low battery. Verify splash appears before shutdown w/o OEM
footer logo.
Change-Id: Ie9a23c0fe9d6b7d314cf4bbe8a8a90eb5689568e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces the `SPLASH_SCREEN_FOOTER` Kconfig option,
enabling a custom footer image or logo on the firmware splash screen.
This provides an additional branding opportunity for device
manufacturers.
`soc_load_logo_by_coreboot()` now conditionally loads and renders
`footer_logo.bmp` when this option is enabled. The footer logo is
positioned at the bottom of the screen.
A new `SPLASH_SCREEN_FOOTER_LOGO_PATH` Kconfig option is added to
define the footer logo's file path. It defaults to a mainboard-specific
location. `Makefile.mk` is updated to ensure this logo is included in
the CBFS.
This additional branding is made possible by rendering bitmaps using
coreboot's native implementation (`USE_COREBOOT_FOR_BMP_RENDERING`).
FSP currently lacks the necessary callbacks to support this feature.
Currently, the OEM footer branding will appear even when the
system is booting in low-battery mode. A planned update will fix this
by exiting early from the boot process, preventing the footer from
showing and conserving power.
BUG=b:423591644
TEST=Able to display custom footer logo on boot.
Change-Id: I57f8af910e8b8f56e8a4a88f8cca6d60fad380b6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch introduces `bmp_load_logo_by_type()` to allow loading a
specific BMP logo from CBFS based on `enum bootsplash_type`.
Now, bmp_load_logo() leverages bmp_load_logo_by_type() with the
system-determined logo type. The new bmp_load_logo_by_type() function
provides a direct interface to load any specified BMP by `enum
bootsplash_type`, which is beneficial for scenarios requiring explicit
logo selection.
BUG=b:423591644
TEST=Able to build and boot google/fatcat. Ensure FW splash screen looks
proper.
Change-Id: I2473f7d48ca2d196ced89d81391cf387627a2f86
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88013
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces an enumerated type `bootsplash_type` to
differentiate between various bootsplash logos, such as
`BOOTSPLASH_LOW_BATTERY` and `BOOTSPLASH_CENTER`.
A `bootsplash_list` array is added to map these types to their
corresponding default filenames. A new function,
`bmp_get_logo_filename`, is provided to retrieve the correct logo
filename based on the specified bootsplash type. This function also
handles overriding the `BOOTSPLASH_CENTER` logo name if
`CONFIG(HAVE_CUSTOM_BMP_LOGO)` is enabled.
The `bmp_load_logo` function is updated to utilize the new
`bootsplash_type` and `bmp_get_logo_filename` to dynamically select the
appropriate logo for display. This change streamlines logo management
and improves flexibility for different boot scenarios.
BUG=b:423591644
TEST=Able to build and boot google/fatcat. FW splash screen looks
proper.
Change-Id: I882deda56b5d30bb15cc7def408c4ea479ffd6ba
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors the bitmap handling in the FSP2.0 driver to
enhance flexibility. Previously, `fsp_convert_bmp_to_gop_blt()`
directly called `bmp_load_logo()`, tying it to specific, predefined
bitmaps like low-battery or OEM splash logos. This prevented its
use for dynamic bitmap files (e.g., brand logos) at runtime.
To address this, `fsp_convert_bmp_to_gop_blt()` no longer handles
bitmap loading. Instead, a new unified API,
`fsp_load_and_convert_bmp_to_gop_blt()`, is introduced for scenarios
where FSP needs to load and convert a bitmap in a single step
(e.g., via its entrypoint).
This change makes `fsp_convert_bmp_to_gop_blt()` a generic API capable
of converting any provided bitmap into a BLT buffer. SoC layers
(like Alder Lake, Meteor Lake, Panther Lake) can now explicitly load
bitmaps and then pass them to `fsp_convert_bmp_to_gop_blt()`, or use
the new `fsp_load_and_convert_bmp_to_gop_blt()` for combined
operations.
Before:
- `soc_load_logo_by_coreboot()` -> `fsp_convert_bmp_to_gop_blt()`
(loads logo internally)
- `soc_load_logo_by_fsp()` -> `fsp_convert_bmp_to_gop_blt()`
(loads logo internally)
**After:**
- `soc_load_logo_by_coreboot()` -> loads logo
-> `fsp_convert_bmp_to_gop_blt()`
- `soc_load_logo_by_fsp()` -> `fsp_load_and_convert_bmp_to_gop_blt()`
BUG=b:423591644
TEST=Able to build and boot google/fatcat. FW splash screen looks
proper.
Change-Id: Ia20e8d42bca6f40c4eb652eb69e3fce84409fc35
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88014
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit introduces PCI device details specific to Wildcat Lake
within the Panther Lake ACPI code, using conditional compilation
to differentiate configurations.
Key changes:
- Create separate ASL files for Panther Lake (`ptl_pcie.asl`) and
Wildcat Lake (`wcl_pcie.asl`) PCIe port configurations.
- Introduce conditional compilation to include Panther Lake or
Wildcat Lake ASL files.
- Wildcat Lake-specific changes compared to Panther Lake:
- Remove following
- PCIe RP : 00:1c.4 to 00:1c.7
: 00:06.2 & 00:06.3
References:
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:394208231
TEST=Build Ocelot and Fatcat and verify it compiles without any error.
Change-Id: I7f6c4f80a811c596824734d749b8d1c4864ccb9b
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88109
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support memory of Micron MT62F512M32D2DR-031 WT:B in mem_parts_used list, and generate SPD ID for this part.
DRAM Part Name Vendor Model Spec ID to assign
MT62F512M32D2DR-031 WT:B Micron LPDDR5 6400 16GB 3 (0011)
BUG=424688292
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/part_id_gen.go ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt"
Change-Id: I310e48a8f240646ec631f0cbc8c0ad0b57e26e0d
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88091
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Skywalker board with MT8189 uses software calibration for ulposc1 (ultra
low power oscillator) and does not support hardware calibration. Remove
the hardware calibration code accordingly.
BUG=b:423516707
BRANCH=none
TEST=build pass and boot up normally.
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: Iea4a0fd8f2c41b54880cef6647e90e0dd1d2bcf1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88151
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Right now dptx_hal_v2 has defined its own
dptx_hal_phy_set_swing_preemphasis, without utilizing the existing
dptx_hal_setswing_preemphasis defined in dptx_hal_common.h.
dptx_hal_v2.c also implements dptx_hal_setswing_preemphasis, but it's
never used.
To reduce duplicate code, rename dptx_hal_setswing_preemphasis in the
common API to dptx_hal_set_swing_preemphasis, and use it for the
dptx_hal_v2 code. Also fix the type for the `lane_count` argument, and
change variable names to make dptx_hal_v1 and dptx_hal_v2 more
consistent.
BUG=none
TEST=emerge-rauru coreboot
BRANCH=none
Change-Id: Id252d29fd1205a949c903d5560f44efc2ff7f477
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88150
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Refactor the MT8196 eDP driver to improve code reusability:
- Move common parts of dp_intf.h to dp_intf_v2.h
- Move common parts of dptx_hal.h to dptx_hal_v2.h
- Move common parts of dptx_reg.h to dptx_v2.h
- Extract shared code from dptx.c to dptx_v2.c
- Extract shared code from dptx_hal.c to dptx_hal_v2.c
- Rename dp_intf.c to dp_intf_v2.c
SoC-specific parts remain in its respective .c and .h files.
BUG=b:400886838
BRANCH=none
TEST=Check the display function on Navi
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ia41f62c0f5f7b5a38d7c5650e6f3a06963cc84a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88149
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The host must initialize necessary settings before
accessing the Realtek EC via EMI.
BUG=b:414474440
TEST=FW_NAME=brox_rtk_ec emerge-brox coreboot chromeos-bootimage
flash to brox board with realtek rts5915
Boot normally and got those message from ap console:
[DEBUG] Google Chrome EC uptime: 107.108 seconds
[DEBUG] Google Chrome AP resets since EC boot: 2
[DEBUG] Google Chrome most recent AP reset causes:
[DEBUG] 10.479: 32775 shutdown: entering G3
[DEBUG] 92.102: 8 reset: during EC initialization
[DEBUG] Google Chrome EC reset flags at last EC boot: watchdog | sysjump
[DEBUG] PNP: 0c09.0 init finished in 81 msecs
Change-Id: I85ad210ccd40097dff552f7e72fe712e33cfd95f
Signed-off-by: Elmo Lan <elmo_lan@realtek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Generate RAM ID for Kingston B3221XM3BDGVI
DRAM Part Name ID to assign
B3221XM3BDGVI 2 (0010)
BUG=b:420797833
BRANCH=firmware-brya-14505.B
TEST=emerge-constitution coreboot
Change-Id: Ic4f92cb7d597a877b693906dee23e1b277fcf122
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Vbt extracted from coreboot-Google_Pujjoga.15217.834.0.bin.
Pujjoga/Pujjogatwin both use same variant dir/same VBT.
TEST=build/boot pujjoga
Change-Id: Ie2054f53563372e9ce7e6692513340a53c35b565
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88094
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because the pujjolo motherboard p-sensor could not recognize, so
I modify the below changes.
1. Update P-sensor I2C bus from 2 to 3.
2. Copy P-sensor parameters from pujjocento.
BUG=b:395763555
BRANCH=none
TEST=Build and verify on pujjolo
Device list:
cat /sys/bus/iio/devices/iio\:device0/name
sx9324
The value of register 01 when away:
i2cget -f -y 13 0x28 01
0x00
The value of register 01 when approaching:
i2cget -f -y 13 0x28 01
0x01
Change-Id: Ia5685ad790949001da7ba793759eb286b8cce1e8
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88104
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable USB3 related functions like usb-a, wwan, wlan.
BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify output of lsusb contains:
us 004 Device 002: ID 8564:4100 Transcend Information, Inc. USB3.1 Hub
Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 003 Device 003: ID 33f8:01a2 Rolling Wireless S.a.r.l. Rolling RW101R-GL Module
Bus 003 Device 005: ID 093a:2516 Pixart Imaging, Inc. USB OPTICAL MOUSE
Bus 003 Device 004: ID 258a:002a SINO WEALTH Thunderobot KG3089
Bus 003 Device 002: ID 8564:4100 Transcend Information, Inc. USB2.1 Hub
Bus 003 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub
Change-Id: Ia9cb6a394169530eb660023998dd92d8691a1607
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88062
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add Ax211 wifi card setting to let wifi function work.
BUG=b:395763555
BRANCH=none
TEST=Insert Ax211 wifi card to MB and boot to OS to connect wifi
successfully.
Change-Id: I061ca0ad54bef23861ad8c937cece72902afff47
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88092
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
