mb/google/nissa/var/yavilla: Add H58G66CK8BX147 to RAM ID table

DRAM Part Name                 ID to assign
H58G66CK8BX147                 1 (0001)

Yavilla use three memory strap pins for RAM_ID definition and it's consumed.
Since the MT62F1G32D4DR-031 WT:B was never used so it's safe to remove.
This CL make the H58G66CK8BX147 to set for RAM_ID1.

BUG=b:425545256
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I9df2710ceb77e4ace6de8976adc1285ef9784c03
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88121
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tony Huang 2025-06-17 14:51:30 +08:00 committed by Subrata Banik
commit 23f5df6eae
3 changed files with 3 additions and 3 deletions

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@ -5,7 +5,7 @@
SPD_SOURCES =
SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B
SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 1(0b0001) Parts = H58G66CK8BX147
SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT
SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 4(0b0100) Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT

View file

@ -5,7 +5,7 @@
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H58G66CK8BX147 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)

View file

@ -10,7 +10,7 @@
# Part Name
MT62F512M32D2DR-031 WT:B
MT62F1G32D4DR-031 WT:B
H58G66CK8BX147
H9JCNNNBK3MLYR-N6E
H58G56AK6BX069
K3LKBKB0BM-MGCP