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soc/mediatek: Unify DPTX swing/preemphasis API

Browse source 
Right now dptx_hal_v2 has defined its own
dptx_hal_phy_set_swing_preemphasis, without utilizing the existing
dptx_hal_setswing_preemphasis defined in dptx_hal_common.h.
dptx_hal_v2.c also implements dptx_hal_setswing_preemphasis, but it's
never used.

To reduce duplicate code, rename dptx_hal_setswing_preemphasis in the
common API to dptx_hal_set_swing_preemphasis, and use it for the
dptx_hal_v2 code. Also fix the type for the `lane_count` argument, and
change variable names to make dptx_hal_v1 and dptx_hal_v2 more
consistent.

BUG=none
TEST=emerge-rauru coreboot
BRANCH=none

Change-Id: Id252d29fd1205a949c903d5560f44efc2ff7f477
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88150
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Vince Liu 2025-06-20 10:44:12 +08:00 • committed by Yidi Lin
commit f63016c36f
7 changed files with 60 additions and 91 deletions
Download patch file Download diff file Expand all files Collapse all files

28
src/soc/mediatek/common/dp/dptx_hal_v1.c
View file

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <console/console.h>
#include <device/mmio.h>
#include <delay.h>
@ -78,24 +79,21 @@ bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp)
return mtk_dp_read(mtk_dp, REG_3414_DP_TRANS_P0) & BIT(2);
}
bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num,
u8 swing_value, u8 preemphasis)
void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count,
u8 *swing_value, u8 *preemphasis)
{
printk(BIOS_DEBUG, "lane(%d), set swing(%#x), emp(%#x)\n",
lane_num, swing_value, preemphasis);
assert(lane_count <= DPTX_LANE_MAX);
if (lane_num >= DPTX_LANE_MAX) {
printk(BIOS_ERR, "invalid lane number: %d\n", lane_num);
return false;
for (int lane = 0; lane < lane_count; lane++) {
printk(BIOS_DEBUG, "lane(%d), set swing(%#x), emp(%#x)\n",
lane, swing_value[lane], preemphasis[lane]);
mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP,
swing_value[lane] << volt_swing[lane].shift,
volt_swing[lane].mask);
mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP,
preemphasis[lane] << volt_preemphasis[lane].shift,
volt_preemphasis[lane].mask);
}
mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP,
swing_value << volt_swing[lane_num].shift,
volt_swing[lane_num].mask);
mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP,
preemphasis << volt_preemphasis[lane_num].shift,
volt_preemphasis[lane_num].mask);
return true;
}
void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp)

35
src/soc/mediatek/common/dp/dptx_hal_v2.c
View file

@ -86,21 +86,19 @@ bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp)
return mtk_dp_read(mtk_dp, REG_364C_AUX_TX_P0) & BIT(15);
}
bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, u8 swing_value,
u8 preemphasis)
void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count,
u8 *swing_value, u8 *preemphasis)
{
assert(lane_num <= DPTX_LANE_MAX);
assert(lane_count <= DPTX_LANE_MAX);
for (int i = 0; i < lane_num; ++i) {
mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i],
swing_value << EDP_TX_LN_VOLT_SWING_VAL_SHIFT |
preemphasis << EDP_TX_LN_PRE_EMPH_VAL_SHIFT,
EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK);
for (int lane = 0; lane < lane_count; lane++) {
printk(BIOS_DEBUG, "lane(%d), set swing(%u), emp(%u)\n",
i, swing_value, preemphasis);
lane, swing_value[lane], preemphasis[lane]);
mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[lane],
swing_value[lane] << EDP_TX_LN_VOLT_SWING_VAL_SHIFT |
preemphasis[lane] << EDP_TX_LN_PRE_EMPH_VAL_SHIFT,
EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK);
}
mtk_dp_mask(mtk_dp, 0x2000, GENMASK(1, 0), GENMASK(1, 0));
return true;
}
void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp)
@ -315,21 +313,6 @@ void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, u8 value)
mtk_dp_mask(mtk_dp, REG_34A4_DP_TRANS_P0, value << 2, BIT(3) | BIT(2));
}
void dptx_hal_phy_set_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, u8 *swing_val,
u8 *preemphasis)
{
assert(lane_count <= DPTX_LANE_MAX);
for (int i = 0; i < lane_count; ++i) {
mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i],
swing_val[i] << EDP_TX_LN_VOLT_SWING_VAL_SHIFT |
preemphasis[i] << EDP_TX_LN_PRE_EMPH_VAL_SHIFT,
EDP_TX_LN_VOLT_SWING_VAL_MASK | EDP_TX_LN_PRE_EMPH_VAL_MASK);
printk(BIOS_DEBUG, "lane(%d), set swing(%u), emp(%u)\n",
i, swing_val[i], preemphasis[i]);
}
}
void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable)
{
u32 val = 0x0;

74
src/soc/mediatek/common/dp/dptx_v1.c
View file

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <commonlib/bsd/helpers.h>
#include <console/console.h>
#include <delay.h>
@ -12,112 +13,101 @@
#include <soc/dp_intf.h>
#include <string.h>
static bool dptx_training_checkswingpre(struct mtk_dp *mtk_dp,
static void dptx_training_checkswingpre(struct mtk_dp *mtk_dp,
u8 target_lane_count,
const u8 *dpcp202_x, u8 *dpcp_buf)
{
bool ret = true;
u8 swing_value, preemphasis;
u8 swing_value[DPTX_LANE_MAX] = {0}, preemphasis[DPTX_LANE_MAX] = {0};
assert(target_lane_count <= DPTX_LANE_MAX);
/* Lane 0 */
if (target_lane_count >= 0x1) {
swing_value = (dpcp202_x[4] & 0x3);
preemphasis = (dpcp202_x[4] & 0xc) >> 2;
/* Adjust the swing and pre-emphasis */
ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE0,
swing_value, preemphasis);
swing_value[0] = (dpcp202_x[4] & 0x3);
preemphasis[0] = (dpcp202_x[4] & 0xc) >> 2;
/*
* Adjust the swing and pre-emphasis done,
* and notify sink side.
*/
dpcp_buf[0] = swing_value | (preemphasis << 3);
dpcp_buf[0] = swing_value[0] | (preemphasis[0] << 3);
/* Max swing reached. */
if (swing_value == DPTX_SWING3)
if (swing_value[0] == DPTX_SWING3)
dpcp_buf[0] |= BIT(2);
/* Max pre-emphasis reached. */
if (preemphasis == DPTX_PREEMPHASIS3)
if (preemphasis[0] == DPTX_PREEMPHASIS3)
dpcp_buf[0] |= BIT(5);
}
/* Lane 1 */
if (target_lane_count >= 0x2) {
swing_value = (dpcp202_x[4] & 0x30) >> 4;
preemphasis = (dpcp202_x[4] & 0xc0) >> 6;
/* Adjust the swing and pre-emphasis */
ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE1,
swing_value, preemphasis);
swing_value[1] = (dpcp202_x[4] & 0x30) >> 4;
preemphasis[1] = (dpcp202_x[4] & 0xc0) >> 6;
/*
* Adjust the swing and pre-emphasis done,
* and notify sink side.
*/
dpcp_buf[1] = swing_value | (preemphasis << 3);
dpcp_buf[1] = swing_value[1] | (preemphasis[1] << 3);
/* Max swing reached. */
if (swing_value == DPTX_SWING3)
if (swing_value[1] == DPTX_SWING3)
dpcp_buf[1] |= BIT(2);
/* Max pre-emphasis reached. */
if (preemphasis == DPTX_PREEMPHASIS3)
if (preemphasis[1] == DPTX_PREEMPHASIS3)
dpcp_buf[1] |= BIT(5);
}
/* Lane 2 and Lane 3 */
if (target_lane_count == 0x4) {
/* Lane 2 */
swing_value = (dpcp202_x[5] & 0x3);
preemphasis = (dpcp202_x[5] & 0x0c) >> 2;
if (target_lane_count >= 0x3) {
assert(target_lane_count == 0x4);
/* Adjust the swing and pre-emphasis */
ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE2,
swing_value, preemphasis);
/* Lane 2 */
swing_value[2] = (dpcp202_x[5] & 0x3);
preemphasis[2] = (dpcp202_x[5] & 0x0c) >> 2;
/*
* Adjust the swing and pre-emphasis done,
* and notify sink side.
*/
dpcp_buf[2] = swing_value | (preemphasis << 3);
dpcp_buf[2] = swing_value[2] | (preemphasis[2] << 3);
/* Max swing reached. */
if (swing_value == DPTX_SWING3)
if (swing_value[2] == DPTX_SWING3)
dpcp_buf[2] |= BIT(2);
/* Max pre-emphasis reached. */
if (preemphasis == DPTX_PREEMPHASIS3)
if (preemphasis[2] == DPTX_PREEMPHASIS3)
dpcp_buf[2] |= BIT(5);
/* Lane 3 */
swing_value = (dpcp202_x[5] & 0x30) >> 4;
preemphasis = (dpcp202_x[5] & 0xc0) >> 6;
/* Adjust the swing and pre-emphasis */
ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE3,
swing_value, preemphasis);
swing_value[3] = (dpcp202_x[5] & 0x30) >> 4;
preemphasis[3] = (dpcp202_x[5] & 0xc0) >> 6;
/*
* Adjust the swing and pre-emphasis done,
* and notify sink side.
*/
dpcp_buf[0x3] = swing_value | (preemphasis << 3);
dpcp_buf[0x3] = swing_value[3] | (preemphasis[3] << 3);
/* Max swing reached. */
if (swing_value == DPTX_SWING3)
if (swing_value[3] == DPTX_SWING3)
dpcp_buf[3] |= BIT(2);
/* Max pre-emphasis reached. */
if (preemphasis == DPTX_PREEMPHASIS3)
if (preemphasis[3] == DPTX_PREEMPHASIS3)
dpcp_buf[3] |= BIT(5);
}
/* Adjust the swing and pre-emphasis */
dptx_hal_set_swing_preemphasis(mtk_dp, target_lane_count,
swing_value, preemphasis);
/* Wait signal stable enough */
mdelay(2);
return ret;
}
static int dptx_train_tps1(struct mtk_dp *mtk_dp, u8 target_lanecount,

2
src/soc/mediatek/common/dp/dptx_v2.c
View file

@ -81,7 +81,7 @@ static void update_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count,
dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00103 + lane, 0x1, &val);
}
dptx_hal_phy_set_swing_preemphasis(mtk_dp, lane_count, swing_val, preemphasis);
dptx_hal_set_swing_preemphasis(mtk_dp, lane_count, swing_val, preemphasis);
}
static void dptx_training_changemode(struct mtk_dp *mtk_dp)

6
src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h
View file

@ -62,8 +62,9 @@ bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd,
u32 dpcd_addr, size_t length, u8 *rx_buf);
bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd,
u32 dpcd_addr, size_t length, u8 *data);
bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num,
u8 swing_value, u8 preemphasis);
void dptx_hal_set_swing_preemphasis(struct mtk_dp *mtk_dp, size_t lane_count,
u8 *swing_value, u8 *preemphasis);
void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp);
u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp);
u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset);
void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask);
@ -73,7 +74,6 @@ void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask);
void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask);
void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val);
void dptx_hal_verify_clock(struct mtk_dp *mtk_dp);
void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp);
void dptx_hal_digital_swreset(struct mtk_dp *mtk_dp);
void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable);
void dptx_hal_hpd_int_en(struct mtk_dp *mtk_dp, bool enable);

2
src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
View file

@ -24,7 +24,5 @@ void dptx_hal_phy_init(struct mtk_dp *mtk_dp);
void dptx_hal_phy_wait_aux_ldo_ready(struct mtk_dp *mtk_dp);
void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable);
void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count);
void dptx_hal_phy_set_swing_preemphasis(struct mtk_dp *mtk_dp, u8 lane_count, u8 *swing_val,
u8 *preemphasis);
#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_V2_H */

4
src/soc/mediatek/mt8196/dptx_hal.c
View file

@ -6,7 +6,7 @@
#include <soc/dptx_hal.h>
#include <soc/dptx_reg.h>
static void dptx_hal_phy_reset_swing_preemphasis(struct mtk_dp *mtk_dp)
void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp)
{
for (int i = 0; i < dptx_hal_driving_offset_size; i++)
mtk_dp_phy_mask(mtk_dp, dptx_hal_driving_offset[i], 0,
@ -37,5 +37,5 @@ void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp)
printk(BIOS_DEBUG, "[eDPTX] DP_PHY_DIG_TX_CTL_0:%#x\n",
mtk_dp_phy_read(mtk_dp, DP_PHY_DIG_TX_CTL_0));
dptx_hal_phy_reset_swing_preemphasis(mtk_dp);
dptx_hal_reset_swing_preemphasis(mtk_dp);
}