soc/mediatek/mt8189: Remove ulposc1 hardware calibration
Skywalker board with MT8189 uses software calibration for ulposc1 (ultra low power oscillator) and does not support hardware calibration. Remove the hardware calibration code accordingly. BUG=b:423516707 BRANCH=none TEST=build pass and boot up normally. Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com> Change-Id: Iea4a0fd8f2c41b54880cef6647e90e0dd1d2bcf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/88151 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
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1 changed files with 4 additions and 32 deletions
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@ -13,9 +13,6 @@
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#include <soc/spm.h>
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#include <soc/spm_mtcmos.h>
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#define ULPOSC1_CHECK_RETRY_COUNT 5
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#define ULPOSC1_HW_CALI_VAL 0x11f10054
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DEFINE_BITFIELD(CLK_EN, 18, 0)
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/* APMIXED, ULPOSC1_CON0 */
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@ -112,35 +109,10 @@ static int pmif_init_ulposc(void)
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int pmif_clk_init(void)
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{
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bool sw_cali = false;
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u32 cali_val;
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for (int i = 0; i < ULPOSC1_CHECK_RETRY_COUNT; i++) {
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cali_val = mt_get_vlpck_freq(FREQ_METER_VLP_OSC_CK) / 1000;
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if (pmif_ulposc_check(cali_val, PMIF_TARGET_FREQ_MHZ) != 0) {
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sw_cali = true;
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break;
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}
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}
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if (sw_cali) {
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/* initialize pmif clock */
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printk(BIOS_INFO, "Using SW calibration!\n");
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if (pmif_init_ulposc())
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return E_NODEV;
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} else {
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printk(BIOS_INFO, "Using HW calibration!\n");
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/* set calibration value */
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cali_val = read32p(ULPOSC1_HW_CALI_VAL);
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printk(BIOS_INFO, "calibration pre value: %#x, PLL_ULPOSC1_CON0 value: %#x\n",
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cali_val, read32(&mtk_vlpsys->vlp_ulposc1_con0));
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SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con0, OSC1_CALI,
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(cali_val >> 1) & 0x7F);
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SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg_30_set, CLK_EN, 0x70000);
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pmif_turn_on_ulposc();
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printk(BIOS_INFO, "PLL_ULPOSC1_CON0: 0x%x\n",
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read32(&mtk_vlpsys->vlp_ulposc1_con0));
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}
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/* initialize pmif clock */
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printk(BIOS_INFO, "Using SW calibration!\n");
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if (pmif_init_ulposc())
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return E_NODEV;
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/* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */
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SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg[0].clr, CLK_PWRAP_ULPOSC_SEL, 0x7,
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