If the directory specified by CONFIG_CPU_INTEL_UCODE_SPLIT_BINARIES does
not contain any files, no build error will occur, and resulting coreboot
image will not include any microcode.
BUG=None
TEST="src/cpu/intel/microcode/Makefile.mk:16: *** "microcode-params is
empty. Ensure CONFIG_CPU_INTEL_UCODE_SPLIT_BINARIES is set correctly and
contains valid files.". Stop."
Change-Id: I095d9a24cb473b528d85bf8325c06fd3dc055b74
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87636
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
According to the MT6359 datasheet, set the RTC EOSC calibration period
to 8 seconds to ensure that the power source VXO22 in the MT6359 meets
the expected power sequence in AP power-off mode.
BUG=b:397292746
BRANCH=none
TEST=build pass & boot pass
Change-Id: I4043f4e82baeb8e0358e74dd6d088895e4deb0f4
Signed-off-by: Shunxi Zhang <ot_shunxi.zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87705
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Don't generate the IVRS ACPI table if the IOMMU PCI device isn't enabled
in the devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5e7f976011da92c0ca69decdca7aa77de24b6a2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
To promote code reuse and maintainability, move mt8196/sspm_sram.c to
common folder. The macro for the register SSPM_SRAM_CON is replaced by
'mtk_spm->sspm_sram_con' since it is already defined in spm.h.
BUG=b:379008996
BRANCH=none
TEST=build passed.
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I71912a23537a8bb26ed431d06123a875b80b8e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87661
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit updates the flash configuration for the Bluey mainboard
to support the 64MB W25Q512NWEIM SPI flash part.
Key changes:
- Kconfig: The `BOARD_ROMSIZE_KB` selection is changed
from 8192 (8MB) to 65536 (64MB).
These changes ensure the firmware is built correctly for the larger
SPI flash and the flash map accurately reflects the hardware.
BUG=b:404985109
TEST=Able to build google/bluey. Running `ls -l` shows that `coreboot.rom` is 64 MB.
Change-Id: I5acd476989e94fba4022eeb4e96fa50b459b5766
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Removed Kconfig selections for `SPI_FLASH_GIGADEVICE` and
`SPI_FLASH_MACRONIX` from `BOARD_GOOGLE_BLUEY_COMMON`.
This change aligns the configuration with hardware plans, as Bluey
is only intended to support Winbond SPI flash parts. Consequently,
support for GigaDevice and Macronix flash chips is removed.
The `SPI_FLASH_WINBOND` selection remains.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Ib5f0d40e45f40e694e36cceade75f1f1ac0349c6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87679
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bluey does not have a Chrome EC. This commit adjusts Kconfig settings
and related code to correctly reflect this hardware characteristic,
ensuring Bluey builds and operates appropriately without an EC.
Key changes:
1. Chrome EC Kconfig Optionalized:
- Unconditional selections for `EC_GOOGLE_CHROMEEC`,
`EC_GOOGLE_CHROMEEC_RTC`, `EC_GOOGLE_CHROMEEC_SPI`,
`EC_GOOGLE_CHROMEEC_SWITCHES` (previously selected via `VBOOT`),
and `RTC` have been removed from `BOARD_GOOGLE_BLUEY_COMMON`.
- These are now grouped under a new Kconfig option
`MAINBOARD_HAS_CHROME_EC` (default 'n'). This ensures
EC-related features/APIs are off by default for Bluey.
2. VBoot Adaptation for no-EC:
- `BOARD_GOOGLE_BLUEY` now selects `VBOOT_NO_BOARD_SUPPORT`.
- VBoot relies on board functions (e.g. WP/recovery switches)
often via an EC. `VBOOT_NO_BOARD_SUPPORT` provides stubs
when an EC is absent, allowing vboot to link.
3. Conditional EC Reset Logic:
- `reset.c`: `do_board_reset()` now calls `google_chromeec_reboot()`
only if `CONFIG(EC_GOOGLE_CHROMEEC)` is enabled. This prevents
errors if called when the EC is not configured.
- (Note: Bluey typically selects `MISSING_BOARD_RESET`, so
`reset.c` may not compile. This change makes `reset.c` safer if
used in a no-EC setup without `MISSING_BOARD_RESET`.)
These modifications ensure that Bluey's firmware configuration aligns
with its actual hardware capabilities, specifically its lack of a
Chrome EC.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Ibee39d76845ce6d9242ade9eacfdb9a8a655c05f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87678
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Bluey board configuration (`BOARD_GOOGLE_BLUEY`) now selects
`MISSING_BOARD_RESET`.
This change is necessary because Bluey does not have a Chrome EC.
Without a Chrome EC, a board-specific `do_board_reset()`
implementation, which often handles system shutdown or reset sequences
by interacting with an EC, is not feasible for Bluey.
As a result of selecting `MISSING_BOARD_RESET`:
- Bluey's `reset.c` is no longer compiled.
- If a board reset is triggered, the system will use the stub
`do_board_reset()` provided when `CONFIG_MISSING_BOARD_RESET`
is enabled.
This aligns Bluey's configuration with its hardware capabilities
regarding system reset.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: I2f770ce9e96544b7e1891a3d8ec84a1313210891
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87677
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a new Kconfig option `MAINBOARD_HAS_GOOGLE_TPM`
for the Bluey mainboard.
Previously, `I2C_TPM`, `MAINBOARD_HAS_TPM2`, and `TPM_GOOGLE_TI50`
were unconditionally selected within `BOARD_GOOGLE_BLUEY_COMMON`.
These selections are now moved under the new `MAINBOARD_HAS_GOOGLE_TPM`
boolean option, which defaults to disabled.
This change allows for more granular control over enabling Google TPM
(aka GSC) support, making it optional for Bluey configurations.
As Bluey (Qualcomm CRD) lacks a Google TPM (GSC), the new
`MAINBOARD_HAS_GOOGLE_TPM` option defaults to 'n'. This ensures
GSC-related features (including `I2C_TPM`, `MAINBOARD_HAS_TPM2`,
and `TPM_GOOGLE_TI50`) are not selected by default for Bluey,
aligning the Kconfig with the hardware capabilities.
BUG=b:404985109
TEST=Able to build google/bluey. Ensure `VBOOT_MOCK_SECDATA` Kconfig
is default enabled for Bluey.
Change-Id: Idc3d998bfc5a747a3068e87fd2f503190a0c1f3f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The `EC_GOOGLE_CHROMEEC_SPI_BUS` Kconfig and the `GPIO_AP_EC_INT`
setup in `chromeos.c` are now dependent on `EC_GOOGLE_CHROMEEC`.
Similarly, the `MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT` Kconfig
and the `GPIO_GSC_AP_INT` setup are now dependent on `TPM_GOOGLE_TI50`.
This ensures that GPIOs are only configured if their respective
features are enabled, preventing potential issues when they are
disabled.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: I44525dd008c42c42aa7e5c4a4f290b09312ed269
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87674
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMBUS_CLK0/DAT0 need to be pulled high on SOC Side according to schematics revision 20241120.
otherwise board cannot enter s0ix due to SMBUS blocking.
BUG=b:403383143
TEST=emerge-fatcat coreboot and machine can enter the s0ix state.
Change-Id: Iac4ca81601331ac35705a73c13ede8efb89ab370
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Move function declarations to dpm_common.h, which is shared for both
dpm_v1 and dpm_v2. Add a new function dpm_init_mcu() to the header to
reduce duplicate code in dpm_v1.c, dpm_v2.c and dpm_4ch.c.
BUG=none
TEST=emerge-skywalker coreboot
BRANCH=none
Change-Id: I8d6318e9c3c4570cb8f3ff64242fc414770db653
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Configure GPIO XHCI_INIT_DONE as output, so that payloads (for example
depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I054dad3783b7fd3c9b00003de9c3333759b8e44a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87657
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the pujjolo variant of nissa reference board by copying the
template files to a new directory named for the variant.
Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.
BUG=b:395763555
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJOLO
Change-Id: Ica959c0e22797ab75606af130fa1adff2b158b1d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87470
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Much like ongoing CFR work, this patch adds support for configuring
certain options (such as iGPU memory allocation, ASPM, S3/s0ix, VT-d) at
runtime, using EDK2 payload.
TEST=Build/boot/toggle coreboot+edk2 on the firewall, test results by
booting Linux.
Change-Id: Id51e704750fd9aa4a8df72804d9205974747d708
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87652
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When using the CFR option backend, a mainboard may want to set the ME
default state to disabled, so add a Kconfig which can be selected to do
so.
Change-Id: I53d88af5e5cc9b7300b847e4aaf8e4cd2ce5bb75
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87649
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I572f119c86ea0e2a16d4bb543bc61afab423d092
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: I2d02184c82ef4874518a3f8e1fe0f5a195188f2a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I083cd4dfc5d4ee7807345c423872d27b66c4edc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87631
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: Ib964e4c2779fe467086681f55136237a69a8f736
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: I08d7c39ba9be92d6a267d20068f41980a5042755
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: Ifa0b567c05e48c4f0f5dc2fc385cf5f82eb083a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the VT-d setting to the option API, so it can be changed at
runtime without recompilation.
Change-Id: I728b71826798eb94c13e54aeadd3ca69c2bf5e8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87626
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add enums for the IGD aperture size and DVMT/stolen memory size, as is
done for newer SoCs. Use these enums rather than their int values
when configuring the IGD.
Change-Id: I369f9c73a00b41b056c89975d4c7e643f1e900c1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87625
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add enums for the IGD aperture size and DVMT/stolen memory size, as is
done for newer SoCs. Use these enums rather than their int values
when configuring the IGD.
Change-Id: I16dbfcd1862ea0c43c62eef59e35ca144a1b2715
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87624
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the IGD UPDs for configuring the DVMT allocated memory and
the aperture size to the option API, so they can be configured via
CMOS/CFR. Default values are set to existing values if option API
is not used.
Add enums to map the DVMT and aperture size UPD values to user-
friendly ones, as was previously done for other SoCs.
Change-Id: Id85e698263b0193d0a83cd4d6ee6c10c89a1d2fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87623
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the IGD UPD for configuring the DVMT allocated memory to the
option API, so it can be configured via CMOS/CFR. Default value is set
to the existing fixed value of 128MB if option API is not used.
Change-Id: I413e958e3c02632c3920b39dd370b89ecc99613f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the IGD UPDs for configuring the DVMT allocated memory and
the aperture size to the option API, so they can be configured via
CMOS/CFR. Default values are set to existing values if option API
is not used.
Add enums to map the DVMT and aperture size UPD values to user-
friendly ones, as was previously done for Alder Lake SoC.
Change-Id: I1c9596d12864bf60449c4e54797a8761e07e2ee4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Hook up the IGD UPDs for configuring the DVMT allocated memory and
the aperture size to the option API, so they can be configured via
CMOS/CFR. Default values are set to existing values if option API
is not used.
Add an enum to map the aperture size UPD values to user-friendly ones,
as was already done for the DVMT size.
Change-Id: I03f100dff2d8a7f6bb87b9860c0be848e8aec61e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87620
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
Change-Id: Iec0b3b10b8cb78014ca1429be73ad2a6646f7de1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
In order to give SMM access to more than 4GiB on x86_64, update the
page table generation in the SMM loader.
Honor CONFIG_CPU_PT_ROM_MAP_GB and map the same amount of the address
space as done in other stages. This is required for SMM trying to access
the SPI BAR in high MMIO on AMD platforms.
TEST=Could access ROM3 BAR at 0xfd00000000 in SMM on AMD/birman+
Change-Id: Iae3dac8d39d3f5e55cc08aa96c8924f6364c5140
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87573
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
The darp10 has a second fan but no dGPU. The NFAN Method must exist, so
use the default hwmon names of "fan1" and "fan2" for labels.
Change-Id: I553deefea374b9dd916be6611850fca61afd490d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Fixes using USB3 devices at USB3 speeds in all ports.
This fix requires `EnableTcssCovTypeA`, which is not available in the
coreboot FSP headers and not available upstream as Intel will not make a
Client FSP release.
Change-Id: I9bc6c5fc4c13bfa2e31ee1ce334b91e151373b6e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
dt_find_node() looks up nodes specified by the `const char **path`
array, without modifying the strings in the array. Therefore, the char
pointers in the array could be changed to const.
Change-Id: I8d330e78d0977bae54996bb622190f6546fcb59f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Let coreboot configure the eSPI GPIOs, to ensure they are correct
rather than letting FSP do it.
Change-Id: I14dc740be9a770b662dd61bfdc4f4ace8973d998
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Hook up the s0ix_enable setting to the option API, so it can be changed
at runtime without recompilation. Default to the value set by the
mainboard.
Change-Id: Icec6dd7d3c80fba5235f9aff5bef8e165302bf2a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87646
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refactors the code by eliminating unnecessary NULL pointer
checks for the `efi_bmp_image_header header` parameter in several
functions. The calling function `fsp_convert_bmp_to_gop_blt` already
verifies that the `header` pointer is not NULL before invoking these
functions, rendering these checks redundant. Similarly, checks for
`adjusted_x` and `adjusted_y` in `calculate_adj_height_width` have been
removed. This streamlines the code and reduces unnecessary operations.
Additionally, the `is_bmp_image_compressed` function has been simplified
for improved readability by directly returning the result of the
compression type comparison.
Change-Id: Ia8afcac0fb21633e379f5d8b9713ba6f8b92c1c8
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87616
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This reverts commit d263e0bd92.
Commit a7eb390796 ("mb/*/*/*.fmd: Start flash at 0") changed the FMAP
to always begin at 0 and not at the x86 MMIO address where it gets
mapped, so the commit reverted by this patch isn't needed any more after
the FMAP change has landed.
Change-Id: I6d866ce3a3395f9fe70c47892a224e89ff89b20e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
amdfwtool is always setting BIOS relative as address_mode for the APOB
NV binary. So instead of giving amdfwtool a memory address we should
give it a flash relative address.
Change-Id: I4596902ca6c9880217247ce6fe96fcb516aec54d
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
1. frequency changes to 366 kHz from 457 kHz
2. tHIGH changes to 0.8 us from 0.514 us
3. tSU:STA changes to 0.68 us from 0.56 us
BUG=b:417375114
BRANCH=firmware-rex-15709.B
TEST=1.emerge-rex coreboot chromeos-bootimage
2.EA is measured and verified by HW
Change-Id: I996885a9acf2eea7f49ecf2fcd4f7d3fda842c8e
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
According to the HW schematics, GPP_A14 should be set as USB_OC1
for the A0 port, but it was found that the USB3_A0 port did not
match the configuration, so this has been corrected.
BUG=b:410481989
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I2fcf15ca008eca6c74f4020c3fa7af8863a56a00
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87637
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Perform early initialization of essential ChromeOS-specific
peripherals and GPIOs within the `bootblock_mainboard_init()`
function. This ensures critical communication paths and
hardware states are configured early in the boot process.
Specifically, this commit:
- Calls `setup_chromeos_gpios()` to configure general AP/EC
interrupts, and conditionally sets up GPIOs for the FPMCU
(reset, boot mode, power rails) and Soundwire amplifiers
(enable pins).
- Initializes the I2C bus for the H1/TPM via `i2c_init()`
when `CONFIG_I2C_TPM` is enabled.
- Initializes the SPI bus for the ChromeEC via `qup_spi_init()`
when `CONFIG_EC_GOOGLE_CHROMEEC` is enabled.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Ic29de4c1f48f33bd1ce6a4385bfc22fdef7ab911
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87642
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add IDs from the EDS, with a couple extras:
- eSPI: EDS says 0x7202, but our boards show 0x7702
- GT: Value changes between 0x7d51 and 0x7dd1 based on DIMMs installed
Change-Id: I8430914edd02954cbb38592bff896733b01c735d
Ref: Intel Arrow Lake-H/U EDS, Volume 1 (#777369, rev 2.0)
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87131
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The Lemur Pro 13 (lemp13) is an Intel Meteor Lake-U based board.
There are 2 variants to differentiate which keyboard design the unit
uses, as they require different EC firmware.
Change-Id: Icac8c7dafd6371881622d797f399f8ddbe13cbce
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Align with Cannon Lake SoCs and make it clear that SMRAM is
and should always be locked. This is cleanup, since Skylake's
Kconfig selects HAVE_SMI_HANDLER.
Change-Id: I136c69ad831d9e16d5034d6e488ee061c9b887f5
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
