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mb/google/brya/var/uldrenite: Fix USB_OC1 for USB3 A0 port

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According to the HW schematics, GPP_A14 should be set as USB_OC1
for the A0 port, but it was found that the USB3_A0 port did not
match the configuration, so this has been corrected.

BUG=b:410481989
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: I2fcf15ca008eca6c74f4020c3fa7af8863a56a00
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87637
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
John Su 2025-05-12 13:52:13 +08:00 • committed by Subrata Banik
commit f0ad05b57e
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/brya/variants/uldrenite/overridetree.cb
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@ -91,7 +91,7 @@ chip soc/intel/alderlake
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # User Facing Camera
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # World Facing Camera
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)"