mb/trulo/var/pujjolo: Create pujjolo variant
Create the pujjolo variant of nissa reference board by copying the template files to a new directory named for the variant. Due to new_variant.py limitation that repo can no longer be used in inside, created this CL manually following google suggestion. BUG=b:395763555 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJOLO Change-Id: Ica959c0e22797ab75606af130fa1adff2b158b1d Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87470 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Luca Lai
Subrata Banik
parent
24757047e5
commit
c443478509
12 changed files with 974 additions and 0 deletions
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@ -490,6 +490,18 @@ config BOARD_GOOGLE_PUJJOGATWIN
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select HAVE_WWAN_POWER_SEQUENCE
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select SOC_INTEL_TWINLAKE
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config BOARD_GOOGLE_PUJJOLO
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select BOARD_GOOGLE_BASEBOARD_TRULO
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select CHROMEOS_WIFI_SAR if CHROMEOS
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select DRIVERS_GENERIC_GPIO_KEYS
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select DRIVERS_INTEL_MIPI_CAMERA
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select DRIVERS_I2C_SX9324
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select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
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select HAVE_WWAN_POWER_SEQUENCE
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION
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select SOC_INTEL_TWINLAKE
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config BOARD_GOOGLE_PUJJONIRU
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select BOARD_GOOGLE_BASEBOARD_NISSA
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select BOARD_ROMSIZE_KB_16384
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@ -869,6 +881,7 @@ config DRIVER_TPM_I2C_BUS
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default 0x0 if BOARD_GOOGLE_MELIKS
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default 0x0 if BOARD_GOOGLE_EPIC
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default 0x0 if BOARD_GOOGLE_PUJJOCENTO
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default 0x0 if BOARD_GOOGLE_PUJJOLO
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config DRIVER_TPM_I2C_ADDR
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hex
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@ -955,6 +968,7 @@ config TPM_TIS_ACPI_INTERRUPT
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default 13 if BOARD_GOOGLE_MELIKS
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default 13 if BOARD_GOOGLE_EPIC
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default 13 if BOARD_GOOGLE_PUJJOCENTO
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default 13 if BOARD_GOOGLE_PUJJOLO
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree_pujjogatwin.cb" if BOARD_GOOGLE_PUJJOGATWIN
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@ -1049,6 +1063,7 @@ config MAINBOARD_PART_NUMBER
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default "Meliks" if BOARD_GOOGLE_MELIKS
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default "Epic" if BOARD_GOOGLE_EPIC
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default "Pujjocento" if BOARD_GOOGLE_PUJJOCENTO
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default "Pujjolo" if BOARD_GOOGLE_PUJJOLO
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config VARIANT_DIR
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default "agah" if BOARD_GOOGLE_AGAH
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@ -1128,6 +1143,7 @@ config VARIANT_DIR
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default "meliks" if BOARD_GOOGLE_MELIKS
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default "epic" if BOARD_GOOGLE_EPIC
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default "pujjocento" if BOARD_GOOGLE_PUJJOCENTO
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default "pujjolo" if BOARD_GOOGLE_PUJJOLO
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config VBOOT
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select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) || BOARD_GOOGLE_RULL
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@ -218,6 +218,9 @@ config BOARD_GOOGLE_PUJJOGA
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config BOARD_GOOGLE_PUJJOGATWIN
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bool "-> Pujjogatwin"
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config BOARD_GOOGLE_PUJJOLO
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bool "-> Pujjolo"
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config BOARD_GOOGLE_ORISA
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bool "-> Orisa"
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9
src/mainboard/google/brya/variants/pujjolo/Makefile.mk
Normal file
9
src/mainboard/google/brya/variants/pujjolo/Makefile.mk
Normal file
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@ -0,0 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += variant.c
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
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245
src/mainboard/google/brya/variants/pujjolo/gpio.c
Normal file
245
src/mainboard/google/brya/variants/pujjolo/gpio.c
Normal file
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@ -0,0 +1,245 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <soc/gpio.h>
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#include <types.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Pad configuration in ramstage for Pujjolo */
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static const struct pad_config override_gpio_table[] = {
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/* E17 : WWAN_RST_L */
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PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG),
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/* A7 : SLP_S0_GATE */
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PAD_CFG_GPO(GPP_A7, 1, DEEP),
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/* A8 : WWAN_RF_DISABLE_ODL */
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PAD_CFG_GPO(GPP_A8, 1, DEEP),
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/* A11 : EN_SPK_PA ==> NC */
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PAD_NC(GPP_A11, NONE),
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/* A12 : NC# ==> SOC_PEN_DETECT_ODL */
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PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_SINGLE),
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/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* A18 : DDSP_HPDB ==> DDI2_HPD */
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/* A19 : NC */
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PAD_NC(GPP_A19, NONE),
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* A20 : HDMI_HPD */
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PAD_NC(GPP_A20, NONE),
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/* A21 : USB_C1_AUX_DC_P */
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PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6),
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/* A22 : USB_C1_AUX_DC_N */
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PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6),
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/* A23 : NC */
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PAD_NC(GPP_A23, NONE),
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/* B2 : NC */
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PAD_NC(GPP_B2, NONE),
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/* B5 : SOC_I2C_SUB_SDA */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
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/* B6 : SOC_I2C_SUB_SCL */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
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/* D6 : SRCCLKREQ1# ==> WWAN_EN */
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PAD_CFG_GPO(GPP_D6, 1, DEEP),
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/* B7 : GPP_B7 ==> NC */
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PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
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/* B8 : WWAN_SAR_DETECT_2_ODL */
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PAD_NC_LOCK(GPP_B8, NONE, LOCK_CONFIG),
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/* B11 : SOC_PMC_PD0_INT_ODL */
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PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
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/* B16 : GPP_B16 ==> I2C_5_SDA */
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PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
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/* B17 : GPP_B17 ==> I2C_5_SCL */
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PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
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/* C1 : SMBDATA ==> USI_RST_L */
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PAD_CFG_GPO(GPP_C1, 1, DEEP),
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/* C4 : TCHSCR_REPORT_EN */
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PAD_CFG_GPO(GPP_C4, 0, DEEP),
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/* C6 : I2C_SOC_PMC_PD_SCL */
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
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/* C7 : I2C_SOC_PMC_PD_SDA */
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
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/* D1 : SEN_MODE2_EC_ISH_INT_ODL */
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PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
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/* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */
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PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
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/* E7 : NC ==> FP_RST_ODL */
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PAD_CFG_GPO_LOCK(GPP_E7, 1, LOCK_CONFIG),
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/* D2 : NC ==> EN_FP_PWR */
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PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
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/* D3 : WCAM_RST_L ==> NC */
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PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
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/* D5 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */
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//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
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/* D13 : UART0_ISH_RX_DBG_TX */
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PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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/* D14 : UART0_ISH_TX_DBG_RX */
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PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
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/* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */
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PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG),
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/* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */
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PAD_CFG_GPO_LOCK(GPP_D16, 1, LOCK_CONFIG),
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/* D17 : NC ==> UART_AP_RX_FP_TX */
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PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
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/* D18 : NC ==> UART_AP_TX_FP_RX */
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PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
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/* D19 : NC */
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PAD_NC(GPP_D19, NONE),
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/* E0 : NC ==> SOC_PEN_DETECT_R_ODL */
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PAD_CFG_GPI_INT(GPP_E0, NONE, PLTRST, EDGE_BOTH),
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/* E4 : WLAN_WWAN_COEX_1 temp out high*/
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PAD_CFG_GPO(GPP_E4, 0, DEEP),
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/* E5 : WLAN_WWAN_COEX_2 temp out high */
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PAD_CFG_GPO(GPP_E5, 0, DEEP),
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/* E11 : TCHSCR_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, INVERT),
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/* E13 : SD_WAKE_N */
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PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG),
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/* E20 : DDP2_CTRLCLK ==> HDMI_DDC_SCL */
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PAD_NC(GPP_E20, NONE),
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/* E21 : DDP2_CTRLDATA ==> HDMI_DDC_SDA_STRAP */
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PAD_NC(GPP_E21, NONE),
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/* E22 : USB_C0_AUX_DC_P */
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PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
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/* E23 : USB_C0_AUX_DC_N */
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PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6),
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/* F11 : NC ==> GSPI_PCH_CLK_FPMCU */
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PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
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/* F12 : WWAN_RST_L ==> GSPI_PCH_DO_FPMCU_DI_R */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
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/* F13 : SOC_PEN_DETECT_R_ODL ==> GSPI_PCH_DI_FPMCU_DO */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
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/* F15 : SOC_PEN_DETECT_ODL ==> FPMCU_INT_L */
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PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PWROK, LEVEL, INVERT),
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/* F16 : NC ==> GSPI_PCH_CS_FPMCU_R_L */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
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/* H8 : I2C_1_SDA */
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PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
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/* H9 : I2C_1_SCL */
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PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
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/* H15 : PD0_SOC_DBG_L */
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PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
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//PAD_CFG_GPI_LOCK(GPP_H15, NONE, LOCK_CONFIG),
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/* H17 : PD1_SOC_DBG_L*/
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//PAD_CFG_GPI_LOCK(GPP_H17, NONE, LOCK_CONFIG),
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PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
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/* H18 : CPU_C10_GATE_L */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
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/* H19 : SOC_I2C_SUB_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
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/* H21 : WWAN_PERST_L */
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PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG),
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/* H23 : WWAN_SAR_DETECT_ODL ==> NC */
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PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG),
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/* R0 : HDA_HP_BCLK_R */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
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/* R1 : HDA_HP_SYNC_R */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1),
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/* R2 : HDA_HP_SDO_R */
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PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1),
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/* R3 : HDA_HP_SDIN0_R */
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PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1),
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/* R4 : DMIC_CLK_A_0A ==> DMIC_UCAM_CLK_R */
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PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
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/* R5 : DMIC_DATA_0A ==> DMIC_UCAM_DATA */
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PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
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/* R6 : DMIC_CLK_A_1A ==> DMIC_WCAM_CLK_R */
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PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
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/* R7 : DMIC_DATA_1A ==> DMIC_WCAM_DATA */
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PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
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/* S0 : NC */
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PAD_NC(GPP_S0, NONE),
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/* S1 : NC */
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PAD_NC(GPP_S1, NONE),
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/* S2 : NC */
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PAD_NC(GPP_S2, NONE),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/*
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* WWAN_EN is asserted in ramstage to meet the 500 ms warm reset toff
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* requirement. WWAN_EN must be asserted before WWAN_RST_L is released
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* (with min delay 0 ms), so this works as long as the pin used for
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* WWAN_EN comes before the pin used for WWAN_RST_L.
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*/
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/* D6 : SRCCLKREQ1# ==> WWAN_EN */
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PAD_CFG_GPO(GPP_D6, 0, DEEP),
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/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
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/*
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* E7 ==> FP_RST_ODL
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* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
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* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
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* early on in bootblock, followed by enabling of power. Reset signal is deasserted
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* later on in ramstage. Since reset signal is asserted in bootblock, it results in
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* FPMCU not working after a S3 resume. This is a known issue.
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*/
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PAD_CFG_GPO(GPP_E7, 0, DEEP),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* E17 : WWAN_RST_L */
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PAD_CFG_GPO(GPP_E17, 0, DEEP),
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/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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};
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/* Pad configuration in romstage for Sundance */
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static const struct pad_config romstage_gpio_table[] = {
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/* E17 : WWAN_RST_L */
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PAD_CFG_GPO(GPP_E17, 1, DEEP),
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/* Enable touchscreen, hold in reset */
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/* C0 : SMBCLK ==> EN_PP3300_TCHSCR */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C1 : SMBDATA ==> USI_RST_L */
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PAD_CFG_TERM_GPO(GPP_C1, 0, UP_20K, DEEP),
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/*
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* E7 ==> FP_RST_ODL
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* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
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* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
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* early on in bootblock, followed by enabling of power. Reset signal is deasserted
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* later on in ramstage. Since reset signal is asserted in bootblock, it results in
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* FPMCU not working after a S3 resume. This is a known issue.
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*/
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PAD_CFG_GPO(GPP_E7, 0, DEEP),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 0, DEEP),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(romstage_gpio_table);
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return romstage_gpio_table;
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
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};
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DECLARE_CROS_GPIOS(cros_gpios);
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78
src/mainboard/google/brya/variants/pujjolo/hda_verb.c
Normal file
78
src/mainboard/google/brya/variants/pujjolo/hda_verb.c
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0257, // Codec Vendor / Device ID: Realtek ALC257
|
||||
0x10ec0257, // Subsystem ID
|
||||
0x00000011, // Number of jacks (NID entries)
|
||||
|
||||
AZALIA_RESET(0x1),
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb table */
|
||||
//AZALIA_SUBVENDOR(0, 0x10ec3a2c),
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
/*
|
||||
* DMIC
|
||||
* Requirement is to use PCH DMIC. Hence,
|
||||
* commented out codec's Internal DMIC.
|
||||
* AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
|
||||
* AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
*/
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x411111F0),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x04A11030),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40579A2D),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
|
||||
//==========Widget node 0x20 - 0 :Hidden register SW reset
|
||||
0x0205001A,
|
||||
0x0204C003,
|
||||
0x0205001A,
|
||||
0x0204C003,
|
||||
//==========Widget node 0x20 - 1 : ClassD 2W
|
||||
0x02050038,
|
||||
0x02047981,
|
||||
0x0205001B,
|
||||
0x02040A4B,
|
||||
//==========Widget node 0x20 - 2
|
||||
0x0205003C,
|
||||
0x02043154,
|
||||
0x0205003C,
|
||||
0x02043114,
|
||||
//==========Widget node 0x20 - 3 :
|
||||
0x02050046,
|
||||
0x02040004,
|
||||
0x05750003,
|
||||
0x057409A3,
|
||||
//==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD
|
||||
0x02050009,
|
||||
0x02046003,
|
||||
0x0205000A,
|
||||
0x02047770,
|
||||
//==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB)
|
||||
0x02050037,
|
||||
0x0204FE15,
|
||||
0x02050030,
|
||||
0x02041000,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
/* Dos beep path - 1 */
|
||||
0x02050010,
|
||||
0x02040020,
|
||||
0x02050036,
|
||||
0x02047151,
|
||||
/* Dos beep path - 2 */
|
||||
0x01470740,
|
||||
0x0143B000,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef __VARIANT_EC_H__
|
||||
#define __VARIANT_EC_H__
|
||||
|
||||
#include <baseboard/ec.h>
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
|
||||
#define WWAN_FCPO GPP_D6
|
||||
#define WWAN_RST GPP_E17
|
||||
#define T2_OFF_MS 20
|
||||
/* FPR feature need add SLP_S0_GATE_R to control.
|
||||
Pujjoniru reference baord did not have HAVE_SLP_S0_GATE.
|
||||
So we add a variant specific S0ix hook to fill the SSDT
|
||||
table to control FPR feature. GPP_A7 pull down when do
|
||||
suspend and pull high when resume. */
|
||||
#define SLP_S0_FP_EN GPP_A7
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# util/spd_tools/bin/part_id_gen adl lp5 src/mainboard/google/brya/variants/pujjolo/memory src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
|
||||
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM-MGCT
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = K3KL8L80CM-MGCT
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = H58G56CK8BX146
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 3(0b0011) Parts = H9JCNNNCP3MLYR-N6E
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# util/spd_tools/bin/part_id_gen adl lp5 src/mainboard/google/brya/variants/pujjolo/memory src/mainboard/google/brya/variants/pujjolo/memory/mem_parts_used.txt
|
||||
|
||||
DRAM Part Name ID to assign
|
||||
K3KL6L60GM-MGCT 0 (0000)
|
||||
K3KL8L80CM-MGCT 1 (0001)
|
||||
H58G56CK8BX146 2 (0010)
|
||||
H9JCNNNCP3MLYR-N6E 3 (0011)
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# This is a CSV file containing a list of memory parts used by this variant.
|
||||
# One part per line with an optional fixed ID in column 2.
|
||||
# Only include a fixed ID if it is required for legacy reasons!
|
||||
# Generated IDs are dependent on the order of parts in this file,
|
||||
# so new parts must always be added at the end of the file!
|
||||
#
|
||||
# Generate an updated Makefile.mk and dram_id.generated.txt by running the
|
||||
# part_id_gen tool from util/spd_tools.
|
||||
# See util/spd_tools/README.md for more details and instructions.
|
||||
|
||||
# Part Name
|
||||
K3KL6L60GM-MGCT
|
||||
K3KL8L80CM-MGCT
|
||||
H58G56CK8BX146
|
||||
H9JCNNNCP3MLYR-N6E
|
||||
543
src/mainboard/google/brya/variants/pujjolo/overridetree.cb
Normal file
543
src/mainboard/google/brya/variants/pujjolo/overridetree.cb
Normal file
|
|
@ -0,0 +1,543 @@
|
|||
fw_config
|
||||
field WWAN 3 4
|
||||
option WWAN_ABSENT 0
|
||||
option LTE_PRESENT 1
|
||||
option 5G_PRESENT 2
|
||||
end
|
||||
field WIFI_SAR_ID 18 21
|
||||
option WIFI_SAR_TABLE_AX211 0
|
||||
option WIFI_SAR_TABLE_AX203 1
|
||||
end
|
||||
end
|
||||
chip soc/intel/alderlake
|
||||
|
||||
# Acoustic settings
|
||||
register "acoustic_noise_mitigation" = "1"
|
||||
register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
|
||||
register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
|
||||
register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
|
||||
register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
|
||||
register "PreWake" = "100"
|
||||
|
||||
register "sagv" = "SaGv_Enabled"
|
||||
|
||||
# SOC Aux orientation override:
|
||||
# This is a bitfield that corresponds to up to 4 TCSS ports.
|
||||
# Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2.
|
||||
# TcssAuxOri = 0101b
|
||||
# Bit0,Bit2 set to "1" indicates no retimer on USBC Ports
|
||||
# Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the
|
||||
# motherboard to USBC connector
|
||||
register "tcss_aux_ori" = "0"
|
||||
|
||||
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
|
||||
register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
|
||||
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB-A1
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UF Camera
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
|
||||
|
||||
#register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN
|
||||
|
||||
# HD Audio
|
||||
register "pch_hda_dsp_enable" = "1"
|
||||
register "pch_hda_audio_link_hda_enable" = "1"
|
||||
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
|
||||
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
|
||||
register "pch_hda_idisp_codec_enable" = "1"
|
||||
register "pch_hda_sdi_enable[0]" = "true"
|
||||
register "pch_hda_sdi_enable[1]" = "true"
|
||||
|
||||
|
||||
# Intel Common SoC Config
|
||||
#+-------------------+---------------------------+
|
||||
#| Field | Value |
|
||||
#+-------------------+---------------------------+
|
||||
#| I2C0 | TPM. Early init is |
|
||||
#| | required to set up a BAR |
|
||||
#| | for TPM communication |
|
||||
#| I2C1 | Touchscreen |
|
||||
#| I2C2 | Sub-board(PSensor)/WCAM |
|
||||
#| I2C5 | Trackpad |
|
||||
#+-------------------+---------------------------+
|
||||
register "common_soc_config" = "{
|
||||
.i2c[0] = {
|
||||
.early_init = 1,
|
||||
.speed = I2C_SPEED_FAST_PLUS,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST_PLUS,
|
||||
.scl_lcnt = 55,
|
||||
.scl_hcnt = 30,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
.i2c[1] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 157,
|
||||
.scl_hcnt = 79,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
.i2c[2] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 157,
|
||||
.scl_hcnt = 79,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
.i2c[4] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 158,
|
||||
.scl_hcnt = 79,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
.i2c[5] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.speed_config[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.scl_lcnt = 158,
|
||||
.scl_hcnt = 79,
|
||||
.sda_hold = 7,
|
||||
}
|
||||
},
|
||||
}"
|
||||
|
||||
register "serial_io_gspi_mode" = "{
|
||||
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
register "serial_io_uart_mode" = "{
|
||||
[PchSerialIoIndexUART0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexUART1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device ref ipu on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "0x50000"
|
||||
register "acpi_name" = ""IPU0""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
|
||||
|
||||
register "cio2_num_ports" = "1"
|
||||
register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used
|
||||
register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0""
|
||||
register "cio2_prt[0]" = "1"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c0 on
|
||||
chip drivers/i2c/tpm
|
||||
register "hid" = ""GOOG0005""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
|
||||
device i2c 50 on end
|
||||
end
|
||||
end #I2C0
|
||||
device ref i2c1 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""GDIX0000""
|
||||
register "generic.desc" = ""Goodix Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
|
||||
register "generic.detect" = "1"
|
||||
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
|
||||
register "generic.enable_delay_ms" = "20"
|
||||
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
|
||||
register "generic.reset_delay_ms" = "180"
|
||||
register "generic.reset_off_delay_ms" = "3"
|
||||
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
|
||||
register "generic.stop_off_delay_ms" = "1"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 5d on end
|
||||
end
|
||||
chip drivers/generic/gpio_keys
|
||||
register "name" = ""PENH""
|
||||
register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E0)"
|
||||
register "key.wake_gpe" = "GPE0_DW0_12"
|
||||
register "key.wakeup_route" = "WAKEUP_ROUTE_SCI"
|
||||
register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
|
||||
register "key.dev_name" = ""EJCT""
|
||||
register "key.linux_code" = "SW_PEN_INSERTED"
|
||||
register "key.linux_input_type" = "EV_SW"
|
||||
register "key.label" = ""pen_eject""
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c2 on
|
||||
chip drivers/i2c/sx9324
|
||||
register "desc" = ""SAR Proximity Sensor""
|
||||
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
|
||||
register "speed" = "I2C_SPEED_FAST"
|
||||
register "uid" = "1"
|
||||
register "reg_gnrl_ctrl0" = "0x16"
|
||||
register "reg_gnrl_ctrl1" = "0x21"
|
||||
register "reg_afe_ctrl0" = "0x00"
|
||||
register "reg_afe_ctrl1" = "0x10"
|
||||
register "reg_afe_ctrl2" = "0x00"
|
||||
register "reg_afe_ctrl3" = "0x00"
|
||||
register "reg_afe_ctrl4" = "0x47"
|
||||
register "reg_afe_ctrl5" = "0x00"
|
||||
register "reg_afe_ctrl6" = "0x00"
|
||||
register "reg_afe_ctrl7" = "0x47"
|
||||
register "reg_afe_ctrl8" = "0x12"
|
||||
register "reg_afe_ctrl9" = "0x08"
|
||||
register "reg_afe_ph0" = "0x3d"
|
||||
register "reg_afe_ph1" = "0x1b"
|
||||
register "reg_afe_ph2" = "0x1f"
|
||||
register "reg_afe_ph3" = "0x3d"
|
||||
register "reg_prox_ctrl0" = "0x0b"
|
||||
register "reg_prox_ctrl1" = "0x0a"
|
||||
register "reg_prox_ctrl2" = "0x90"
|
||||
register "reg_prox_ctrl3" = "0x60"
|
||||
register "reg_prox_ctrl4" = "0x0c"
|
||||
register "reg_prox_ctrl5" = "0x00"
|
||||
register "reg_prox_ctrl6" = "0x19"
|
||||
register "reg_prox_ctrl7" = "0x58"
|
||||
register "reg_adv_ctrl0" = "0x00"
|
||||
register "reg_adv_ctrl1" = "0x00"
|
||||
register "reg_adv_ctrl2" = "0x00"
|
||||
register "reg_adv_ctrl3" = "0x00"
|
||||
register "reg_adv_ctrl4" = "0x00"
|
||||
register "reg_adv_ctrl5" = "0x05"
|
||||
register "reg_adv_ctrl6" = "0x00"
|
||||
register "reg_adv_ctrl7" = "0x00"
|
||||
register "reg_adv_ctrl8" = "0x00"
|
||||
register "reg_adv_ctrl9" = "0x00"
|
||||
register "reg_adv_ctrl10" = "0x00"
|
||||
register "reg_adv_ctrl11" = "0x00"
|
||||
register "reg_adv_ctrl12" = "0x00"
|
||||
register "reg_adv_ctrl13" = "0x00"
|
||||
register "reg_adv_ctrl14" = "0x80"
|
||||
register "reg_adv_ctrl15" = "0x0c"
|
||||
register "reg_adv_ctrl16" = "0x08"
|
||||
register "reg_adv_ctrl17" = "0x56"
|
||||
register "reg_adv_ctrl18" = "0x33"
|
||||
register "reg_adv_ctrl19" = "0x00"
|
||||
register "reg_adv_ctrl20" = "0x00"
|
||||
|
||||
register "ph0_pin" = "{1, 3, 3}"
|
||||
register "ph1_pin" = "{3, 2, 1}"
|
||||
register "ph2_pin" = "{3, 3, 1}"
|
||||
register "ph3_pin" = "{1, 3, 3}"
|
||||
register "ph01_resolution" = "1024"
|
||||
register "ph23_resolution" = "1024"
|
||||
register "startup_sensor" = "1"
|
||||
register "ph01_proxraw_strength" = "3"
|
||||
register "ph23_proxraw_strength" = "2"
|
||||
register "avg_pos_strength" = "256"
|
||||
register "cs_idle_sleep" = ""hi-z""
|
||||
register "int_comp_resistor" = ""lowest""
|
||||
register "input_precharge_resistor_ohms" = "4000"
|
||||
register "input_analog_gain" = "1"
|
||||
device i2c 28 on end
|
||||
end
|
||||
end
|
||||
device ref i2c4 on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = ""OVTI8856""
|
||||
register "acpi_uid" = "0"
|
||||
register "acpi_name" = ""CAM0""
|
||||
register "chip_name" = ""Ov 8856 Camera""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
|
||||
register "has_power_resource" = "1"
|
||||
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
|
||||
|
||||
register "ssdb.lanes_used" = "2"
|
||||
register "ssdb.link_used" = "1"
|
||||
register "ssdb.vcm_type" = "0x0C"
|
||||
register "vcm_name" = ""VCM0""
|
||||
register "num_freq_entries" = "2"
|
||||
register "link_freq[0]" = "720000000"
|
||||
register "link_freq[1]" = "360000000"
|
||||
register "remote_name" = ""IPU0""
|
||||
|
||||
#Controls
|
||||
register "clk_panel.clks[0].clknum" = "IMGCLKOUT_3"
|
||||
register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
|
||||
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X
|
||||
register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X
|
||||
register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "5"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
|
||||
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
|
||||
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
|
||||
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)"
|
||||
register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "4"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
|
||||
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)"
|
||||
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 10 on
|
||||
end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "3"
|
||||
register "acpi_name" = ""VCM0""
|
||||
register "chip_name" = ""DW AF DAC""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
|
||||
|
||||
register "vcm_compat" = ""dongwoon,dw9714""
|
||||
register "has_power_resource" = "true"
|
||||
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
|
||||
|
||||
# Controls
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X
|
||||
register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X
|
||||
|
||||
# _ON
|
||||
register "on_seq.ops_cnt" = "2"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
|
||||
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
|
||||
|
||||
# _OFF
|
||||
register "off_seq.ops_cnt" = "2"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 0C on
|
||||
end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "acpi_uid" = "1"
|
||||
register "acpi_name" = ""NVM0""
|
||||
register "chip_name" = ""GT24C08""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_NVM"
|
||||
register "has_power_resource" = "true"
|
||||
register "max_dstate_for_probe" = "ACPI_DEVICE_SLEEP_D3_COLD"
|
||||
|
||||
# Controls
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X
|
||||
|
||||
# _ON
|
||||
register "on_seq.ops_cnt" = "1"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
|
||||
|
||||
# _OFF
|
||||
register "off_seq.ops_cnt" = "1"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
register "nvm_size" = "0x2000"
|
||||
register "nvm_pagesize" = "1"
|
||||
register "nvm_readonly" = "1"
|
||||
register "nvm_width" = "0x10"
|
||||
register "nvm_compat" = ""atmel,24c08""
|
||||
|
||||
device i2c 50 on
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref i2c5 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "wake" = "GPE0_DW2_14"
|
||||
register "detect" = "1"
|
||||
device i2c 15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""SYNA0000""
|
||||
register "generic.cid" = ""ACPI0C50""
|
||||
register "generic.desc" = ""Synaptics Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "generic.wake" = "GPE0_DW2_14"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 0x2c on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""FCAL0000""
|
||||
register "generic.cid" = ""ACPI0C50""
|
||||
register "generic.desc" = ""Focal Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
|
||||
register "generic.wake" = "GPE0_DW2_14"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 0x38 on end
|
||||
end
|
||||
end
|
||||
device ref ish on
|
||||
chip drivers/intel/ish
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref ufs on end
|
||||
device ref igpu on
|
||||
end
|
||||
device ref pcie_rp4 on
|
||||
# PCIe 4 WLAN
|
||||
register "pch_pcie_rp[PCH_RP(4)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_DW1_03"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp7 on
|
||||
# Enable SD Card PCIE 7 using clk 3
|
||||
register "pch_pcie_rp[PCH_RP(7)]" = "{
|
||||
.clk_src = 3,
|
||||
.clk_req = 3,
|
||||
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
|
||||
register "srcclk_pin" = "3"
|
||||
device generic 0 on end
|
||||
end
|
||||
end #PCIE7 SD card
|
||||
device ref pch_espi on
|
||||
chip ec/google/chromeec
|
||||
use conn0 as mux_conn[0]
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port1 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C1 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref tcss_usb3_port2 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C1 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref usb2_port2 on end
|
||||
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A1 (DB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb2_port4 on end
|
||||
end
|
||||
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port5 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 UFC""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 WFC""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port8 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""CNVi Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "reset_gpio" =
|
||||
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A1 (DB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref hda on
|
||||
chip drivers/sof
|
||||
register "spkr_tplg" = "max98360a"
|
||||
register "jack_tplg" = "nau8825"
|
||||
register "mic_tplg" = "_4ch"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref gspi1 on
|
||||
chip drivers/spi/acpi
|
||||
register "name" = ""CRFP""
|
||||
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "uid" = "1"
|
||||
register "compat_string" = ""google,cros-ec-spi""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
|
||||
register "wake" = "GPE0_DW2_15"
|
||||
register "has_power_resource" = "1"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
|
||||
register "enable_delay_ms" = "3"
|
||||
device spi 0 on
|
||||
end
|
||||
end # FPMCU
|
||||
end
|
||||
end
|
||||
end
|
||||
19
src/mainboard/google/brya/variants/pujjolo/variant.c
Normal file
19
src/mainboard/google/brya/variants/pujjolo/variant.c
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <chip.h>
|
||||
#include <fw_config.h>
|
||||
#include <soc/gpio_soc_defs.h>
|
||||
#include <intelblocks/graphics.h>
|
||||
#include <acpi/acpi.h>
|
||||
#include <acpi/acpigen.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
|
||||
void variant_generate_s0ix_hook(enum s0ix_entry entry)
|
||||
{
|
||||
if (entry == S0IX_ENTRY)
|
||||
acpigen_soc_clear_tx_gpio(SLP_S0_FP_EN);
|
||||
else if (entry == S0IX_EXIT)
|
||||
acpigen_soc_set_tx_gpio(SLP_S0_FP_EN);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue