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soc/mediatek/mt8189: Add SPI driver support

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Add SPI controller driver code with support for 6 buses (SPI0 to SPI5).

BUG=b:379008996
BRANCH=none
TEST=build pass

Signed-off-by: Alex Gan <ot_alex.gan@mediatek.corp-partner.google.com>
Change-Id: I313eddefed466a5182b6e48ac1900674cc06b0b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit is contained in:
Alex Gan 2024-12-20 17:46:43 +08:00 • committed by Matt DeVillier
commit f1f58b20b9
4 changed files with 105 additions and 1 deletions
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2
src/soc/mediatek/mt8189/Makefile.mk
View file

@ -5,7 +5,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8189),y)
all-y += ../common/flash_controller.c
all-y += ../common/gpio.c ../common/gpio_op.c ../common/gpio_eint_v2.c gpio.c gpio_eint.c
all-y += ../common/i2c.c ../common/i2c_common.c i2c.c
all-$(CONFIG_SPI_FLASH) += spi.c
all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
all-y += ../common/timer_prepare.c timer.c
all-y += ../common/uart.c

6
src/soc/mediatek/mt8189/include/soc/addressmap.h
View file

@ -44,6 +44,12 @@ enum {
DPM_DM_SRAM_BASE2 = IO_PHYS + 0x00A20000,
DPM_CFG_BASE2 = IO_PHYS + 0x00A40000,
UART0_BASE = IO_PHYS + 0x01001000,
SPI0_BASE = IO_PHYS + 0x01010800,
SPI1_BASE = IO_PHYS + 0x01011800,
SPI2_BASE = IO_PHYS + 0x01012800,
SPI3_BASE = IO_PHYS + 0x01013800,
SPI4_BASE = IO_PHYS + 0x01014800,
SPI5_BASE = IO_PHYS + 0x01015800,
SFLASH_REG_BASE = IO_PHYS + 0x01018000,
PERI_AO_BCRM_BASE = IO_PHYS + 0x01035000,
PERICFG_AO_BASE = IO_PHYS + 0x01036000,

16
src/soc/mediatek/mt8189/include/soc/spi.h
View file

@ -8,6 +8,22 @@
#ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__
#define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__
#include <soc/spi_common.h>
#define SPI_BUS_NUMBER 6
#define GET_SCK_REG(x) ((x)->spi_cfg2_reg)
#define GET_TICK_DLY_REG(x) ((x)->spi_cmd_reg)
DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0)
DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16)
DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 31, 16)
DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 15, 0)
DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0)
DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8)
DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 31, 16)
DEFINE_BITFIELD(SPI_TICK_DLY, 28, 22)
/* Initialize SPI NOR Flash Controller */
void mtk_snfc_init(void);

82
src/soc/mediatek/mt8189/spi.c
View file

@ -10,6 +10,72 @@
#include <soc/spi.h>
#include <spi_flash.h>
struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = {
{
.regs = (void *)SPI0_BASE,
.cs_gpio = GPIO(SPIM0_CSB),
},
{
.regs = (void *)SPI1_BASE,
.cs_gpio = GPIO(SPIM1_CSB),
},
{
.regs = (void *)SPI2_BASE,
.cs_gpio = GPIO(SPIM2_CSB),
},
{
.regs = (void *)SPI3_BASE,
.cs_gpio = GPIO(GPIO00),
},
{
.regs = (void *)SPI4_BASE,
.cs_gpio = GPIO(GPIO04),
},
{
.regs = (void *)SPI5_BASE,
.cs_gpio = GPIO(GPIO08),
},
};
static const struct pad_func pad_funcs[SPI_BUS_NUMBER][4] = {
{
PAD_FUNC_DOWN(SPIM0_MISO, SPIM0_MI),
PAD_FUNC_GPIO(SPIM0_CSB),
PAD_FUNC_DOWN(SPIM0_MOSI, SPIM0_MO),
PAD_FUNC_DOWN(SPIM0_CLK, SPIM0_CLK),
},
{
PAD_FUNC_DOWN(SPIM1_MISO, SPIM1_MI),
PAD_FUNC_GPIO(SPIM1_CSB),
PAD_FUNC_DOWN(SPIM1_MOSI, SPIM1_MO),
PAD_FUNC_DOWN(SPIM1_CLK, SPIM1_CLK),
},
{
PAD_FUNC_DOWN(SPIM2_MISO, SPIM2_MI),
PAD_FUNC_GPIO(SPIM2_CSB),
PAD_FUNC_DOWN(SPIM2_MOSI, SPIM2_MO),
PAD_FUNC_DOWN(SPIM2_CLK, SPIM2_CLK),
},
{
PAD_FUNC_DOWN(GPIO03, SPIM3_A_MI),
PAD_FUNC_GPIO(GPIO00),
PAD_FUNC_DOWN(GPIO02, SPIM3_A_MO),
PAD_FUNC_DOWN(GPIO01, SPIM3_A_CLK),
},
{
PAD_FUNC_DOWN(GPIO07, SPIM4_A_MI),
PAD_FUNC_GPIO(GPIO04),
PAD_FUNC_DOWN(GPIO06, SPIM4_A_MO),
PAD_FUNC_DOWN(GPIO05, SPIM4_A_CLK),
},
{
PAD_FUNC_DOWN(GPIO11, SPIM5_A_MI),
PAD_FUNC_GPIO(GPIO08),
PAD_FUNC_DOWN(GPIO10, SPIM5_A_MO),
PAD_FUNC_DOWN(GPIO09, SPIM5_A_CLK),
},
};
static const struct pad_func nor_pinmux[4] = {
PAD_FUNC(SPINOR_CK, SPINOR_CK, GPIO_PULL_DOWN),
PAD_FUNC(SPINOR_CS, SPINOR_CS, GPIO_PULL_UP),
@ -23,12 +89,28 @@ void mtk_snfc_init(void)
mtk_snfc_init_pad_func(&nor_pinmux[i], GPIO_DRV_8_MA);
}
void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select)
{
assert(bus < SPI_BUS_NUMBER);
const struct pad_func *ptr;
ptr = pad_funcs[bus];
for (unsigned int i = 0; i < ARRAY_SIZE(pad_funcs[0]); i++)
gpio_set_mode(ptr[i].gpio, ptr[i].func);
}
static const struct spi_ctrlr spi_flash_ctrlr = {
.max_xfer_size = 65535,
.flash_probe = mtk_spi_flash_probe,
};
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
{
.ctrlr = &spi_ctrlr,
.bus_start = 0,
.bus_end = SPI_BUS_NUMBER - 1,
},
{
.ctrlr = &spi_flash_ctrlr,
.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,