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mb/google/fatcat/var/felino: Add pull high setting on GPP_C03/GPP_C04 in gpio.c

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SMBUS_CLK0/DAT0 need to be pulled high on SOC Side according to schematics revision 20241120.
otherwise board cannot enter s0ix due to SMBUS blocking.

BUG=b:403383143
TEST=emerge-fatcat coreboot and machine can enter the s0ix state.

Change-Id: Iac4ca81601331ac35705a73c13ede8efb89ab370
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Tongtong Pan 2025-05-14 09:09:47 +08:00 • committed by Subrata Banik
commit 4e8ea210bb
1 changed files with 5 additions and 4 deletions
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9
src/mainboard/google/fatcat/variants/felino/gpio.c
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@ -106,10 +106,11 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C01, NONE),
/* GPP_C02: GPPC_C2_SMB_ALERT_N */
PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1),
/* FIXME: b/417841162 */
/* GPP_C03: SMBUS_CLK0 */
PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1),
/* GPP_C04: SMBUS_DAT0 */
PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1),
/* GPP_C05: GPPC_C5 */
PAD_NC(GPP_C05, NONE),
/* GPP_C06: NC */
@ -410,9 +411,9 @@ static const struct pad_config early_gpio_table[] = {
/* Pad configuration in romstage */
static const struct pad_config romstage_gpio_table[] = {
/* GPP_C03: GPP_C0_SMBCLK */
PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1),
/* GPP_C04: GPP_C0_SMBDATA */
PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1),
};
const struct pad_config *variant_gpio_table(size_t *num)