soc/intel/tigerlake: Hook up IGD config to option API
Hook up the IGD UPDs for configuring the DVMT allocated memory and the aperture size to the option API, so they can be configured via CMOS/CFR. Default values are set to existing values if option API is not used. Add enums to map the DVMT and aperture size UPD values to user- friendly ones, as was previously done for Alder Lake SoC. Change-Id: I1c9596d12864bf60449c4e54797a8761e07e2ee4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This commit is contained in:
parent
d930a3542c
commit
dcbb5771c9
2 changed files with 45 additions and 1 deletions
|
|
@ -115,6 +115,42 @@ enum ddi_port_config {
|
|||
DDI_PORT_CFG_MIPI_DSI = 2,
|
||||
};
|
||||
|
||||
enum igd_dvmt50_pre_alloc {
|
||||
IGD_SM_0MB = 0x00,
|
||||
IGD_SM_32MB = 0x01,
|
||||
IGD_SM_64MB = 0x02,
|
||||
IGD_SM_96MB = 0x03,
|
||||
IGD_SM_128MB = 0x04,
|
||||
IGD_SM_160MB = 0x05,
|
||||
IGD_SM_4MB = 0xF0,
|
||||
IGD_SM_8MB = 0xF1,
|
||||
IGD_SM_12MB = 0xF2,
|
||||
IGD_SM_16MB = 0xF3,
|
||||
IGD_SM_20MB = 0xF4,
|
||||
IGD_SM_24MB = 0xF5,
|
||||
IGD_SM_28MB = 0xF6,
|
||||
IGD_SM_36MB = 0xF8,
|
||||
IGD_SM_40MB = 0xF9,
|
||||
IGD_SM_44MB = 0xFA,
|
||||
IGD_SM_48MB = 0xFB,
|
||||
IGD_SM_52MB = 0xFC,
|
||||
IGD_SM_56MB = 0xFD,
|
||||
IGD_SM_60MB = 0xFE,
|
||||
};
|
||||
|
||||
enum igd_aperture_size {
|
||||
IGD_AP_SZ_128MB = 0x00,
|
||||
IGD_AP_SZ_256MB = 0x01,
|
||||
IGD_AP_SZ_512MB = 0x02,
|
||||
/*
|
||||
* Values below require use of above 4G MMIO,
|
||||
* otherwise FSP will hang
|
||||
*/
|
||||
IGD_AP_SZ_4G_512MB = 0x03,
|
||||
IGD_AP_SZ_4G_1024MB = 0x07,
|
||||
IGD_AP_SZ_4G_2048MB = 0x15,
|
||||
};
|
||||
|
||||
struct soc_intel_tigerlake_config {
|
||||
/* Common struct containing soc config data required by common code */
|
||||
struct soc_intel_common_config common_soc_config;
|
||||
|
|
|
|||
|
|
@ -29,7 +29,15 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
|
|||
|
||||
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
|
||||
|
||||
/* If IGD is enabled, set IGD stolen size to 60MB. Otherwise, skip IGD init in FSP */
|
||||
if (m_cfg->InternalGfx) {
|
||||
/* IGD is enabled, set IGD stolen size to 60MB. */
|
||||
m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB);
|
||||
m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
|
||||
} else {
|
||||
/* IGD is disabled, skip IGD init in FSP. */
|
||||
m_cfg->IgdDvmt50PreAlloc = 0;
|
||||
}
|
||||
|
||||
m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
|
||||
|
||||
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue