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soc/intel/alderlake: Hook up IGD config to option API

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Hook up the IGD UPDs for configuring the DVMT allocated memory and
the aperture size to the option API, so they can be configured via
CMOS/CFR. Default values are set to existing values if option API
is not used.

Add an enum to map the aperture size UPD values to user-friendly ones,
as was already done for the DVMT size.

Change-Id: I03f100dff2d8a7f6bb87b9860c0be848e8aec61e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87620
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2025-05-10 10:28:52 -05:00
commit d930a3542c
2 changed files with 15 additions and 1 deletions
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13
src/soc/intel/alderlake/chip.h
View file

@ -483,6 +483,19 @@ struct soc_intel_alderlake_config {
IGD_SM_60MB = 0xFE,
} igd_dvmt50_pre_alloc;
enum {
IGD_AP_SZ_128MB = 0x00,
IGD_AP_SZ_256MB = 0x01,
IGD_AP_SZ_512MB = 0x02,
/*
* Values below require use of above 4G MMIO,
* otherwise FSP will hang
*/
IGD_AP_SZ_4G_512MB = 0x03,
IGD_AP_SZ_4G_1024MB = 0x07,
IGD_AP_SZ_4G_2048MB = 0x15,
} igd_aperture_size;
bool skip_ext_gfx_scan;
bool eist_enable;
bool enable_c6dram;

3
src/soc/intel/alderlake/romstage/fsp_params.c
View file

@ -134,7 +134,8 @@ static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
if (m_cfg->InternalGfx) {
/* IGD is enabled, set IGD stolen size to 60MB. */
m_cfg->IgdDvmt50PreAlloc = IGD_SM_60MB;
m_cfg->IgdDvmt50PreAlloc = get_uint_option("igd_dvmt_prealloc", IGD_SM_60MB);
m_cfg->ApertureSize = get_uint_option("igd_aperture_size", IGD_AP_SZ_256MB);
/* DP port config */
m_cfg->DdiPortAConfig = config->ddi_portA_config;
m_cfg->DdiPortBConfig = config->ddi_portB_config;