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mb/google/bluey: Initialize I2C, SPI, and GPIOs in bootblock

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Perform early initialization of essential ChromeOS-specific
peripherals and GPIOs within the `bootblock_mainboard_init()`
function. This ensures critical communication paths and
hardware states are configured early in the boot process.

Specifically, this commit:
- Calls `setup_chromeos_gpios()` to configure general AP/EC
  interrupts, and conditionally sets up GPIOs for the FPMCU
  (reset, boot mode, power rails) and Soundwire amplifiers
  (enable pins).
- Initializes the I2C bus for the H1/TPM via `i2c_init()`
  when `CONFIG_I2C_TPM` is enabled.
- Initializes the SPI bus for the ChromeEC via `qup_spi_init()`
  when `CONFIG_EC_GOOGLE_CHROMEEC` is enabled.

BUG=b:404985109
TEST=Able to build google/bluey.

Change-Id: Ic29de4c1f48f33bd1ce6a4385bfc22fdef7ab911
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87642
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2025-05-12 15:32:47 +05:30
commit 1140891211
2 changed files with 24 additions and 2 deletions
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12
src/mainboard/google/bluey/bootblock.c
View file

@ -1,8 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <soc/qupv3_i2c_common.h>
#include <soc/qcom_qup_se.h>
#include <soc/qupv3_spi_common.h>
#include "board.h"
void bootblock_mainboard_init(void)
{
/* Placeholder */
setup_chromeos_gpios();
if (CONFIG(I2C_TPM))
i2c_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); /* H1/TPM I2C */
if (CONFIG(EC_GOOGLE_CHROMEEC))
qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz); /* EC SPI */
}

14
src/mainboard/google/bluey/chromeos.c
View file

@ -2,14 +2,26 @@
#include <boot/coreboot_tables.h>
#include <bootmode.h>
#include "board.h"
#include <drivers/tpm/cr50.h>
#include "board.h"
void setup_chromeos_gpios(void)
{
gpio_input_pullup(GPIO_AP_EC_INT);
gpio_input_irq(GPIO_GSC_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP);
if (CONFIG(MAINBOARD_HAS_FINGERPRINT)) {
gpio_output(GPIO_FP_RST_L, 0);
if (CONFIG(MAINBOARD_HAS_FINGERPRINT_VIA_SPI)) {
gpio_output(GPIO_FPMCU_BOOT0, 0);
gpio_output(GPIO_EN_FP_RAILS, 0);
gpio_input_irq(GPIO_FPMCU_INT, IRQ_TYPE_LEVEL, GPIO_PULL_UP);
}
}
gpio_output(GPIO_SNDW_AMP_0_ENABLE, 0);
gpio_output(GPIO_SNDW_AMP_1_ENABLE, 0);
}
void fill_lb_gpios(struct lb_gpios *gpios)