mb/google/brya/var/uldrenite: Enable PMC, HECI and SRAM devices

Referencing the baseboard PnP settings for Uldrenite.

BUG=b:380789023
TEST=emerge-nissa coreboot

Change-Id: Icd537fd5b6bfa589931633b72477414098523b54
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>

src/mainboard/google/brya/variants/uldrenite/overridetree.cb

@@ -120,6 +120,10 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
 
+	# FIXME: To be enabled in future based on PNP impact data.
+	# Disable Package C-state demotion for nissa baseboard.
+	register "disable_package_c_state_demotion" = "true"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
@@ -448,6 +452,9 @@ chip soc/intel/alderlake
 				device generic 0 alias rp2_wwan on end
 			end
 		end # PCIE2 WWAN card
+		device ref shared_sram on end
+		device ref heci1 on end
+		device ref pmc hidden end
 		device ref emmc on end
 		device ref uart0 on end
 		device ref pch_espi on