mb/google/nissa/var/rull: For probe, change unprovisioned to unknown

The nissa project fw branch is more suitable for compatibility with unknown, so the compatible methods of wifi and ssd are replaced.

BUG=b:383675207
BRANCH=None
TEST=emerge-nissa coreboot chromeos-bootimage

Change-Id: Id2415d18c635dece94500f511bccdc9d2b69d1b4
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Rui Zhou 2024-12-12 17:24:39 +08:00 committed by Subrata Banik
commit 0ce153c8df
2 changed files with 14 additions and 10 deletions

View file

@ -6,6 +6,7 @@ fw_config
field WIFI 8 9
option WIFI_CNVI_WIFI6E 0
option WIFI_PCIE_WIFI7 1
option WIFI_UNKNOWN 2
end
end
@ -393,8 +394,8 @@ chip soc/intel/alderlake
register "add_acpi_dma_property" = "true"
device generic 0 on end
end
probe WIFI WIFI_CNVI_WIFI6E
probe unprovisioned
probe WIFI WIFI_CNVI_WIFI6E
probe WIFI WIFI_UNKNOWN
end
device ref pcie_rp4 on
# PCIe 4 WLAN
@ -416,7 +417,7 @@ chip soc/intel/alderlake
device generic 0 on end
end
probe WIFI WIFI_PCIE_WIFI7
probe unprovisioned
probe WIFI WIFI_UNKNOWN
end
device ref pch_espi on
chip ec/google/chromeec
@ -518,7 +519,10 @@ chip soc/intel/alderlake
register "desc" = ""PCIe Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
device ref usb2_port8 on end
device ref usb2_port8 on
probe WIFI WIFI_PCIE_WIFI7
probe WIFI WIFI_UNKNOWN
end
end
chip drivers/usb/acpi
register "desc" = ""CNVi Bluetooth""
@ -526,6 +530,7 @@ chip soc/intel/alderlake
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
device ref usb2_port10 on
probe WIFI WIFI_CNVI_WIFI6E
probe WIFI WIFI_UNKNOWN
end
end
chip drivers/usb/acpi
@ -569,15 +574,14 @@ chip soc/intel/alderlake
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
register "srcclk_pin" = "1"
device generic 0 on
probe STORAGE STORAGE_NVME
probe unprovisioned
end
device generic 0 on end
end
probe STORAGE STORAGE_NVME
probe STORAGE STORAGE_UNKNOWN
end
device ref emmc on
probe STORAGE STORAGE_EMMC
probe unprovisioned
probe STORAGE STORAGE_UNKNOWN
end
device ref hda on
chip drivers/sof

View file

@ -18,7 +18,7 @@ const char *get_wifi_sar_cbfs_filename(void)
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{
if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E))) {
if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI6E)) || fw_config_probe(FW_CONFIG(WIFI, WIFI_UNKNOWN))) {
printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n");
config->cnvi_bt_core = true;
config->cnvi_bt_audio_offload = true;