mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682)

1. Enable HDA driver
2. Add spkr_tplg = max98360a
3. Add jack_tplg = rt5682

BUG=b:380789023
TEST=emerge-nissa coreboot

Change-Id: I8f78a8641de23eadb03348a31574045702b40554
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>

src/mainboard/google/brya/Kconfig

@@ -616,6 +616,7 @@ config BOARD_GOOGLE_ULDRENITE
 	select HAVE_PCIE_WWAN
 	select HAVE_WWAN_POWER_SEQUENCE
 	select DRIVERS_WWAN_FM350GL
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 
 config BOARD_GOOGLE_VELL
 	select BOARD_GOOGLE_BASEBOARD_BRYA

src/mainboard/google/brya/variants/uldrenite/Makefile.mk

@@ -4,3 +4,5 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
 ramstage-y += gpio.c
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c

src/mainboard/google/brya/variants/uldrenite/overridetree.cb

@@ -78,6 +78,13 @@ chip soc/intel/alderlake
 	# Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
 	register "tcss_aux_ori" = "0"
 
+	# HD Audio
+	register "pch_hda_dsp_enable" = "1"
+	register "pch_hda_audio_link_hda_enable" = "1"
+	register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
+	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
+	register "pch_hda_idisp_codec_enable" = "1"
+
 	# Configure external V1P05/Vnn/VnnSx Rails
 	register "ext_fivr_settings" = "{
 		.configure_ext_fivr = 1,
@@ -448,5 +455,13 @@ chip soc/intel/alderlake
 				device pnp 0c09.0 on end
 			end
 		end
+		device ref hda on
+			chip drivers/sof
+				register "spkr_tplg" = "max98360a"
+				register "jack_tplg" = "rt5682"
+				register "mic_tplg" = "_2ch_pdm0"
+				device generic 0 on end
+			end
+		end
 	end
 end