Per discussion in CB:87660, this is another approach to fix duplicate
ACPI device GFX0.
The following GFX ACPI device is already declared in nissa/devicetree
by CB:83071, it declare a ACPI gfx device as below:
device ref igpu on
register "panel_cfg" = "{
.up_delay_ms = 200,
.down_delay_ms = 50,
.cycle_delay_ms = 500,
.backlight_on_delay_ms = 1,
.backlight_off_delay_ms = 200,
.backlight_pwm_hz = 200,
}"
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
It will generate an ACPI \_SB.PCI0.GFX0 device.
However, some Nissa projects re-select DRIVERS_GFX_GENERIC in their
overridetree, which results in the generation of a second
\_SB.PCI0.GFX0. This duplication causes iasl to fail when disassembling
the SSDT table.
Error message from iasl:
File appears to be binary: found 7485 non-ASCII characters, disassembling
Binary file appears to be a valid ACPI table, disassembling
Input file SSDT, Length 0x4A03 (18947) bytes
ACPI: SSDT 0x0000000000000000 004A03 (v02 COREv4 COREBOOT 00000000 CORE 20230628)
Pass 1 parse of [SSDT]
Firmware Error (ACPI): Failure creating named object [\_SB.PCI0.GFX0._DOD], AE_ALREADY_EXISTS (20200925/dswload-387)
ACPI Error: AE_ALREADY_EXISTS, During name lookup/catalog (20200925/psobject-264)
Could not parse ACPI tables, AE_ALREADY_EXISTS
BUG=none
TEST=disassembling SSDT on pujjoniru successfully
Change-Id: I16e9875c12b4e8e42214da5972bed6a02c5567f4
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87745
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit introduces support for LP5 and DDR5 memory configurations
on ocelot. It adds board IDs for ocelot and integrates new memory
settings within the variant parameters. The new memory configuration
includes settings related to early command training and LP5/DDR5
specific training parameters.
LP5 memory configuration includes detailed DQ and DQS mapping for
different DDR channels. This facilitates accurate routing of signals
and initialization of memory. Additionally, SPD information retrieval
is adapted to accommodate DDR5-specific settings, such as DIMM module
topology and SMBus addresses.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: I828b1944d5a0d7f58aa8f545d567b1bb1b0da5ae
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87684
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Fn key on pujjocento emits a scancode of 94 (0x5e).
BUG=b:417141058
TEST=Flash Pujjocento, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: If8ad29fccbd7c088ee793f3261df0b0999f25765
Signed-off-by: lizheng <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
RTL8111 was occasionally not detected after reboot. This change
moves the configuration of the ISOLATE_ODL pin to high earlier
in the sequence to ensure the device is properly visible during
PCIe bus enumeration.
BUG=b:407469351
TEST=Verified that the Ethernet NIC is enumerated after reboot.
before:
[DEBUG] PCI: 00:1c.0 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:1c.0
[DEBUG] PCI: pci_scan_bus for bus 01
[INFO ] PCI: Static device PCI: 01:00.0 not found, disabling it.
[DEBUG] GENERIC: 0.0 enabled
[WARN ] PCI: Leftover static devices:
[WARN ] PCI: 01:00.0
[WARN ] PCI: Check your devicetree.cb.
[DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 34 msecs
after:
[DEBUG] PCI: 00:1c.0 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:1c.0
[DEBUG] PCI: pci_scan_bus for bus 01
[SPEW ] PCI: 01:00.0 [10ec/0000] ops
[DEBUG] PCI: 01:00.0 [10ec/8168] enabled
[DEBUG] GENERIC: 0.0 enabled
[INFO ] Enabling Common Clock Configuration
[INFO ] L1 Sub-State supported from root port 28
[INFO ] L1 Sub-State Support = 0xf
[INFO ] CommonModeRestoreTime = 0x96
[INFO ] Power On Value = 0xf, Power On Scale = 0x1
[INFO ] ASPM: Enabled L1
[INFO ] PCIe: Max_Payload_Size adjusted to 128
[INFO ] PCI: 01:00.0: Enabled LTR
[INFO ] PCI: 01:00.0: Programmed LTR max latencies
[DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 68 msecs
Change-Id: Idc0eb453c342828e0e8886ca5cacea8d7efcc437
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87734
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
The FW_CONFIG feature is not used on mc_rpl. Delete the related source
file and the reference to it in Makefile.
Change-Id: Ifec1efc239801205f1aec2095082c8f744f84a55
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Since this board comes with a fixed SoC (Raptor Lake with ADL-P PCH),
there is no need to have multiple different gpio configuration files and
devicetree files. This patch deletes the unneeded files and adopts
Makefile.mk to not use them.
Change-Id: Iced9d695e3f21dec260795bb651109ff9b2beb59
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This mainboard neither uses Chrome OS nor has any embedded controller
available. This patch removes all references from the build in this
regard. This also requires some refactoring in board_id.c.
Change-Id: If834480fbdac4b4843c265a257d3a77678f56aab
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87666
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename chromeos.fmd to mc_rpl.fmd and adjust the flash layout settings
to match the needs of this board. There is e.g. no A/B scheme used and
CSME stitching is done externally, therefore no detailed CSME partitions
are required at all.
Change-Id: I6389960d816c5f1a4690a965961301d3797305ff
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This patch adds a new mainboard called 'mc_rpl' which is based on the
Intel Alder Lake RVP. Only the needed changes are made in this patch in
order to make it compile with proper names. Follow-up patches will
tailor it more towards the real mainboard hardware.
Change-Id: Ic0caa621350848d459def6044ca0a6dfd88f873f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87664
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
update GPP_R4/GPP_R5 setting based on pujjocento proto schematic.
BUG=b:409752486
TEST=emerge-nissa sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: I5a2926a074e801162972d950c62002352fb5cf6e
Signed-off-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87756
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The E7240 actually has a 8MiB + 4MiB flash configuration, not 8MiB.
Change-Id: I14f0c8f6f0c0dfebf41294812b1f4e131eaa18d0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit overrides the `logo_valignment` setting in the
`common_soc_config` for the Ocelot board variant, similar to
https://review.coreboot.org/c/coreboot/+/87453.
The vertical alignment for the firmware splash screen logo is now set to
`FW_SPLASH_VALIGNMENT_MIDDLE`, which places the top edge of the logo at
the vertical midpoint of the screen.
Change-Id: I29f08d31d325304f7532ed37f9cf3d5ef0bb88ff
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit removes the `device ref npk on end` from the
`overridetree.cb` files for ocelot, similar to -
commit 85c65b0c20 (mb/google/fatcat: Remove NPK device from fatcat and francka variants)
This effectively disables the NPK device for these configurations
(because `npk` is default set to disable).
Change-Id: Iee1509f44f6543c23f9633ccd8d35d4a7e37b89e
Signed-off-by: Avi Uday <aviuday@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87753
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
crrev/c/5828162 introduced vccin_aux_imon_iccmax parameter for each variant to override the VccInAuxImonIccImax FSP parameter to follow its VCCANA power rail design.
Since meliks adopts external VR design for VCCANA power rail, set it to 25A to follow the guidance in RDC#646929 Power Map.
BUG=b:409205469
TEST=Built and boot
Verified maximum 5% of 3D mark score improvement on N250 SKU
Change-Id: I58786493098c787d402c85ce7167319285af7488
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87704
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, it was found that the GPP_D2 and GPP_D18 pins affect power
consumption during S0ix. After discussion with the hardware team,
since the motherboard is shared across different platforms and these
two pins are unused on the Chrome platform, they will be set to NC.
Measurements have shown that this change effectively improves power
consumption.
Due to some pins changes for next phase, the modifications are listed
below for reference.
Follow the GPIO table updated on 05/19.
GPP_D2 : GPO -> NC
GPP_D14:
Current phase: GPO -> NC
Next phase : FUNC1 (UART0_ISH)
GPP_D18:
Current phase: FUNC2 (UART1_ISH)
Next phase : GPO -> NC
BUG=b:411554553
TEST=improve 375mW-->143mW
Change-Id: I3c788ed4e2ff3e5d49008c03a895d13549d5c79b
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87709
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes an unnecessary space in the Kconfig name
for BOARD_GOOGLE_FELINO.
Change-Id: I49044a49fcef914b2e11d3c2eeefe6b6b082d8c1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87749
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add initialization of DPM driver for DRAM low power mode.
BUG=b:379008996
BRANCH=none
TEST=Boot up pass and see log
3200 LPDDR5 chan0(x16) rank0: memory test pass
3200 LPDDR5 chan0(x16) rank1: memory test pass
3200 LPDDR5 chan1(x16) rank0: memory test pass
3200 LPDDR5 chan1(x16) rank1: memory test pass
Signed-off-by: Mike Lin <mike.lin@mediatek.corp-partner.google.com>
Change-Id: I3b72b892d56623e7f3ec2dccfad073a908b51119
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87663
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The file was mistakenly left out in the version that got merged, so
internal speakers wouldn't work.
TEST=Boot to Windows 11 and verify internal speakers work
Change-Id: I5529030bb91a41236772ac410096dc6bff00dd32
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87306
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the flash configuration for the Bluey mainboard
to support the 64MB W25Q512NWEIM SPI flash part.
Key changes:
- Kconfig: The `BOARD_ROMSIZE_KB` selection is changed
from 8192 (8MB) to 65536 (64MB).
These changes ensure the firmware is built correctly for the larger
SPI flash and the flash map accurately reflects the hardware.
BUG=b:404985109
TEST=Able to build google/bluey. Running `ls -l` shows that `coreboot.rom` is 64 MB.
Change-Id: I5acd476989e94fba4022eeb4e96fa50b459b5766
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Removed Kconfig selections for `SPI_FLASH_GIGADEVICE` and
`SPI_FLASH_MACRONIX` from `BOARD_GOOGLE_BLUEY_COMMON`.
This change aligns the configuration with hardware plans, as Bluey
is only intended to support Winbond SPI flash parts. Consequently,
support for GigaDevice and Macronix flash chips is removed.
The `SPI_FLASH_WINBOND` selection remains.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Ib5f0d40e45f40e694e36cceade75f1f1ac0349c6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87679
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bluey does not have a Chrome EC. This commit adjusts Kconfig settings
and related code to correctly reflect this hardware characteristic,
ensuring Bluey builds and operates appropriately without an EC.
Key changes:
1. Chrome EC Kconfig Optionalized:
- Unconditional selections for `EC_GOOGLE_CHROMEEC`,
`EC_GOOGLE_CHROMEEC_RTC`, `EC_GOOGLE_CHROMEEC_SPI`,
`EC_GOOGLE_CHROMEEC_SWITCHES` (previously selected via `VBOOT`),
and `RTC` have been removed from `BOARD_GOOGLE_BLUEY_COMMON`.
- These are now grouped under a new Kconfig option
`MAINBOARD_HAS_CHROME_EC` (default 'n'). This ensures
EC-related features/APIs are off by default for Bluey.
2. VBoot Adaptation for no-EC:
- `BOARD_GOOGLE_BLUEY` now selects `VBOOT_NO_BOARD_SUPPORT`.
- VBoot relies on board functions (e.g. WP/recovery switches)
often via an EC. `VBOOT_NO_BOARD_SUPPORT` provides stubs
when an EC is absent, allowing vboot to link.
3. Conditional EC Reset Logic:
- `reset.c`: `do_board_reset()` now calls `google_chromeec_reboot()`
only if `CONFIG(EC_GOOGLE_CHROMEEC)` is enabled. This prevents
errors if called when the EC is not configured.
- (Note: Bluey typically selects `MISSING_BOARD_RESET`, so
`reset.c` may not compile. This change makes `reset.c` safer if
used in a no-EC setup without `MISSING_BOARD_RESET`.)
These modifications ensure that Bluey's firmware configuration aligns
with its actual hardware capabilities, specifically its lack of a
Chrome EC.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Ibee39d76845ce6d9242ade9eacfdb9a8a655c05f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87678
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Bluey board configuration (`BOARD_GOOGLE_BLUEY`) now selects
`MISSING_BOARD_RESET`.
This change is necessary because Bluey does not have a Chrome EC.
Without a Chrome EC, a board-specific `do_board_reset()`
implementation, which often handles system shutdown or reset sequences
by interacting with an EC, is not feasible for Bluey.
As a result of selecting `MISSING_BOARD_RESET`:
- Bluey's `reset.c` is no longer compiled.
- If a board reset is triggered, the system will use the stub
`do_board_reset()` provided when `CONFIG_MISSING_BOARD_RESET`
is enabled.
This aligns Bluey's configuration with its hardware capabilities
regarding system reset.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: I2f770ce9e96544b7e1891a3d8ec84a1313210891
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87677
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces a new Kconfig option `MAINBOARD_HAS_GOOGLE_TPM`
for the Bluey mainboard.
Previously, `I2C_TPM`, `MAINBOARD_HAS_TPM2`, and `TPM_GOOGLE_TI50`
were unconditionally selected within `BOARD_GOOGLE_BLUEY_COMMON`.
These selections are now moved under the new `MAINBOARD_HAS_GOOGLE_TPM`
boolean option, which defaults to disabled.
This change allows for more granular control over enabling Google TPM
(aka GSC) support, making it optional for Bluey configurations.
As Bluey (Qualcomm CRD) lacks a Google TPM (GSC), the new
`MAINBOARD_HAS_GOOGLE_TPM` option defaults to 'n'. This ensures
GSC-related features (including `I2C_TPM`, `MAINBOARD_HAS_TPM2`,
and `TPM_GOOGLE_TI50`) are not selected by default for Bluey,
aligning the Kconfig with the hardware capabilities.
BUG=b:404985109
TEST=Able to build google/bluey. Ensure `VBOOT_MOCK_SECDATA` Kconfig
is default enabled for Bluey.
Change-Id: Idc3d998bfc5a747a3068e87fd2f503190a0c1f3f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The `EC_GOOGLE_CHROMEEC_SPI_BUS` Kconfig and the `GPIO_AP_EC_INT`
setup in `chromeos.c` are now dependent on `EC_GOOGLE_CHROMEEC`.
Similarly, the `MAINBOARD_GPIO_PIN_FOR_GSC_AP_INTERRUPT` Kconfig
and the `GPIO_GSC_AP_INT` setup are now dependent on `TPM_GOOGLE_TI50`.
This ensures that GPIOs are only configured if their respective
features are enabled, preventing potential issues when they are
disabled.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: I44525dd008c42c42aa7e5c4a4f290b09312ed269
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87674
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMBUS_CLK0/DAT0 need to be pulled high on SOC Side according to schematics revision 20241120.
otherwise board cannot enter s0ix due to SMBUS blocking.
BUG=b:403383143
TEST=emerge-fatcat coreboot and machine can enter the s0ix state.
Change-Id: Iac4ca81601331ac35705a73c13ede8efb89ab370
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Configure GPIO XHCI_INIT_DONE as output, so that payloads (for example
depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I054dad3783b7fd3c9b00003de9c3333759b8e44a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87657
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the pujjolo variant of nissa reference board by copying the
template files to a new directory named for the variant.
Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.
BUG=b:395763555
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJOLO
Change-Id: Ica959c0e22797ab75606af130fa1adff2b158b1d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87470
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Much like ongoing CFR work, this patch adds support for configuring
certain options (such as iGPU memory allocation, ASPM, S3/s0ix, VT-d) at
runtime, using EDK2 payload.
TEST=Build/boot/toggle coreboot+edk2 on the firewall, test results by
booting Linux.
Change-Id: Id51e704750fd9aa4a8df72804d9205974747d708
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87652
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The darp10 has a second fan but no dGPU. The NFAN Method must exist, so
use the default hwmon names of "fan1" and "fan2" for labels.
Change-Id: I553deefea374b9dd916be6611850fca61afd490d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Fixes using USB3 devices at USB3 speeds in all ports.
This fix requires `EnableTcssCovTypeA`, which is not available in the
coreboot FSP headers and not available upstream as Intel will not make a
Client FSP release.
Change-Id: I9bc6c5fc4c13bfa2e31ee1ce334b91e151373b6e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Let coreboot configure the eSPI GPIOs, to ensure they are correct
rather than letting FSP do it.
Change-Id: I14dc740be9a770b662dd61bfdc4f4ace8973d998
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
1. frequency changes to 366 kHz from 457 kHz
2. tHIGH changes to 0.8 us from 0.514 us
3. tSU:STA changes to 0.68 us from 0.56 us
BUG=b:417375114
BRANCH=firmware-rex-15709.B
TEST=1.emerge-rex coreboot chromeos-bootimage
2.EA is measured and verified by HW
Change-Id: I996885a9acf2eea7f49ecf2fcd4f7d3fda842c8e
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
According to the HW schematics, GPP_A14 should be set as USB_OC1
for the A0 port, but it was found that the USB3_A0 port did not
match the configuration, so this has been corrected.
BUG=b:410481989
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I2fcf15ca008eca6c74f4020c3fa7af8863a56a00
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87637
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Perform early initialization of essential ChromeOS-specific
peripherals and GPIOs within the `bootblock_mainboard_init()`
function. This ensures critical communication paths and
hardware states are configured early in the boot process.
Specifically, this commit:
- Calls `setup_chromeos_gpios()` to configure general AP/EC
interrupts, and conditionally sets up GPIOs for the FPMCU
(reset, boot mode, power rails) and Soundwire amplifiers
(enable pins).
- Initializes the I2C bus for the H1/TPM via `i2c_init()`
when `CONFIG_I2C_TPM` is enabled.
- Initializes the SPI bus for the ChromeEC via `qup_spi_init()`
when `CONFIG_EC_GOOGLE_CHROMEEC` is enabled.
BUG=b:404985109
TEST=Able to build google/bluey.
Change-Id: Ic29de4c1f48f33bd1ce6a4385bfc22fdef7ab911
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87642
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Lemur Pro 13 (lemp13) is an Intel Meteor Lake-U based board.
There are 2 variants to differentiate which keyboard design the unit
uses, as they require different EC firmware.
Change-Id: Icac8c7dafd6371881622d797f399f8ddbe13cbce
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Since commit bb66d07d41
"soc/amd/common: Always use genoa SPI MMAP driver" the ROM size can be
actually be greater than 16MiB on all AMD platforms without seeing a
boot failure. Since still only 16MiB of the SPI flash are MMAPed,
the FMAP should not be extended, and if so should only contain non x86
firmwares in the upper 16MiB of flash.
Now that common code supports ROM_SIZE greater than 16MiB select the
correct BOARD_ROMSIZE_KB for each mainboard.
Change-Id: Icdce01bddbc4873ba42ceddcda6d9075f5a42914
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
