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mb/var/uldrenite: Make two pins NC to reduce S0ix power consumption

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Currently, it was found that the GPP_D2 and GPP_D18 pins affect power
consumption during S0ix. After discussion with the hardware team,
since the motherboard is shared across different platforms and these
two pins are unused on the Chrome platform, they will be set to NC.
Measurements have shown that this change effectively improves power
consumption.

Due to some pins changes for next phase, the modifications are listed
below for reference.

Follow the GPIO table updated on 05/19.

GPP_D2         : GPO -> NC
GPP_D14:
  Current phase: GPO -> NC
  Next phase   : FUNC1 (UART0_ISH)
GPP_D18:
  Current phase: FUNC2 (UART1_ISH)
  Next phase   : GPO -> NC

BUG=b:411554553
TEST=improve 375mW-->143mW

Change-Id: I3c788ed4e2ff3e5d49008c03a895d13549d5c79b
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87709
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Su 2025-05-16 13:23:30 +08:00 • committed by Subrata Banik
commit ccd4d1d1db
2 changed files with 7 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

8
src/mainboard/google/brya/variants/uldrenite/gpio.c
View file

@ -121,8 +121,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_D0, 1, DEEP),
/* D1 : ISH_GP1 ==> SOC_GSEN2_INT# */
PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
/* D2 : ISH_GP2 ==> TOUCH_SCREEN_DET# */
PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
/* D2 : ISH_GP2 ==> NC */
PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
/* D3 : NC ==> PHY_SHUTTER_DET */
PAD_CFG_GPO_LOCK(GPP_D3, 1, LOCK_CONFIG),
/* D4 : NC ==> WCAM_FW_PROTECT */
@ -153,8 +153,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
/* D17 : NC */
PAD_NC(GPP_D17, NONE),
/* D18 : LCD_CBL_DET# */
PAD_CFG_GPO(GPP_D18, 1, DEEP),
/* D18 : LCD_CBL_DET# ==> NC */
PAD_NC(GPP_D18, NONE),
/* D19 : I2S_MCLK1_OUT ==> NC */
PAD_NC(GPP_D19, NONE),

6
src/mainboard/google/brya/variants/uldrenite/variant.c
View file

@ -61,11 +61,11 @@ static const struct pad_config ish_uart0_disable_pads[] = {
static const struct pad_config switch_ish_uart1_pads[] = {
/* D13 : UART0_ISH_RXD ==> NC */
PAD_NC(GPP_D13, NONE),
/* D14 : UART0_ISH_TXD ==> LCD_CBL_DET# */
PAD_CFG_GPO(GPP_D14, 1, DEEP),
/* D14 : UART0_ISH_TXD ==> NC */
PAD_NC(GPP_D14, NONE),
/* D17 : NC ==> UART1_ISH_RDX */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
/* D18 : LCD_CBL_DET# ==> UART1_ISH_TDX */
/* D18 : NC ==> UART1_ISH_TDX */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2),
};