mb/siemens/mc_rpl: Remove unused gpio and devicetree files
Since this board comes with a fixed SoC (Raptor Lake with ADL-P PCH), there is no need to have multiple different gpio configuration files and devicetree files. This patch deletes the unneeded files and adopts Makefile.mk to not use them. Change-Id: Iced9d695e3f21dec260795bb651109ff9b2beb59 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Werner Zeh
Matt DeVillier
parent
8fdf8694e3
commit
7fbea3175d
7 changed files with 1 additions and 1419 deletions
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@ -3,14 +3,9 @@
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subdirs-y += spd
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bootblock-y += bootblock.c
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ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
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bootblock-y += early_gpio_n.c
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ramstage-y += gpio_n.c
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else
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bootblock-y += early_gpio.c
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ramstage-y += gpio.c
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endif
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ramstage-y += gpio.c
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romstage-y += romstage_fsp_params.c
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romstage-y += board_id.c
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romstage-y += memory.c
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@ -1,406 +0,0 @@
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fw_config
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field AUDIO 8 10
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option NONE 0
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option ADL_MAX98373_ALC5682I_I2S 1
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end
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end
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chip soc/intel/alderlake
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_D"
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register "pmc_gpe0_dw2" = "GPP_E"
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# FSP configuration
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register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0
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register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
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register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A port 1
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register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # Type-A port 2
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register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1
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register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2
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register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-A port 2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WLAN
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# Sagv Configuration
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register "sagv" = "SaGv_Enabled"
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# Enable CNVi Bluetooth
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register "cnvi_bt_core" = "true"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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#Enable PCH PCIE RP 4 using CLK 5
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register "pch_pcie_rp[PCH_RP(4)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_L1_2,
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}"
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# Enable PCH PCIE RP 5 using CLK 2
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 2,
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.clk_req = 2,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_L1_2,
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}"
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# Enable PCH PCIE RP 9 using CLK 3
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 3,
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.clk_req = 3,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_L1_2,
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}"
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#Enable PCH PCIE RP 10 using CLK 1
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register "pch_pcie_rp[PCH_RP(10)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
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.PcieRpL1Substates = L1_SS_L1_2,
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}"
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# Hybrid storage mode
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register "hybrid_storage_mode" = "true"
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# Enable CPU PCIE RP 1 using CLK 0
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 0,
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.clk_src = 0,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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# Enable EDP in PortA
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register "ddi_portA_config" = "1"
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# Enable HDMI in Port B
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register "ddi_ports_config" = "{
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[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
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}"
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# TCSS USB3
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register "tcss_aux_ori" = "0"
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register "s0ix_enable" = "true"
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "serial_io_gspi_mode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoPci,
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[PchSerialIoIndexGSPI1] = PchSerialIoPci,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
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}"
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register "serial_io_gspi_cs_mode" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 1,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "serial_io_gspi_cs_state" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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[PchSerialIoIndexGSPI3] = 0,
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}"
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register "serial_io_uart_mode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# HD Audio
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register "pch_hda_dsp_enable" = "1"
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register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
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register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
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register "pch_hda_idisp_codec_enable" = "1"
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# Intel Common SoC Config
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register "common_soc_config" = "{
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.gspi[1] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device ref pcie5_0 on end
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device ref igpu on end
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device ref dtt on end
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device ref ipu on
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chip drivers/intel/mipi_camera
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register "acpi_uid" = "0x50000"
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register "acpi_name" = ""IPU0""
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register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
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register "cio2_num_ports" = "2"
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register "cio2_lanes_used" = "{2,2}"
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register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
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register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
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register "cio2_prt[0]" = "2"
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register "cio2_prt[1]" = "1"
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device generic 0 on end
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end
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end
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device ref pcie4_0 on end
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device ref pcie4_1 on end
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp1 on end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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register "type" = "UPC_TYPE_HUB"
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""TypeC Port 1""
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""TypeC Port 2""
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device ref tcss_usb3_port2 on end
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end
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end
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end
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end
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device ref tcss_dma0 on end
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device ref xhci on
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chip drivers/usb/acpi
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register "desc" = ""Root Hub""
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register "type" = "UPC_TYPE_HUB"
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port10 on end
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end
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end
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end
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end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref i2c0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_H3_IRQ)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on
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probe AUDIO ADL_MAX98373_ALC5682I_I2S
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end
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end
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "0"
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register "imon_slot_no" = "1"
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register "uid" = "0"
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register "desc" = ""Right Speaker Amp""
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register "name" = ""MAXR""
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device i2c 31 on
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probe AUDIO ADL_MAX98373_ALC5682I_I2S
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end
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end
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chip drivers/i2c/max98373
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register "vmon_slot_no" = "2"
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register "imon_slot_no" = "3"
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register "uid" = "1"
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register "desc" = ""Left Speaker Amp""
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register "name" = ""MAXL""
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device i2c 32 on
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probe AUDIO ADL_MAX98373_ALC5682I_I2S
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end
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end
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chip drivers/i2c/hid
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register "generic.hid" = ""WACOM PWB-D893""
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register "generic.desc" = ""WACOM Touchscreen""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)"
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register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)"
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register "generic.enable_delay_ms" = "1"
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register "generic.reset_delay_ms" = "300"
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register "generic.has_power_resource" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 0a on end
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end
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chip drivers/i2c/hid
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register "generic.hid" = ""ELAN0000""
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register "generic.desc" = ""ELAN Touchpad""
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register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D11_IRQ)"
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register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H1)"
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register "generic.wake" = "GPE0_DW1_11"
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register "generic.detect" = "1"
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register "generic.has_power_resource" = "1"
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device i2c 15 on end
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end
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end
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device ref i2c1 on
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chip drivers/intel/mipi_camera
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register "acpi_hid" = ""OVTI5675""
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register "acpi_uid" = "0"
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register "acpi_name" = ""CAM0""
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register "chip_name" = ""Ov 5675 Camera""
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register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
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register "ssdb.lanes_used" = "2"
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register "ssdb.vcm_type" = "0x0C"
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register "vcm_name" = ""VCM0""
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register "num_freq_entries" = "1"
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register "link_freq[0]" = "450000000"
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register "remote_name" = ""IPU0""
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register "has_power_resource" = "true"
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#Controls
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register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
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register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
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register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
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register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
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#_ON
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register "on_seq.ops_cnt" = "4"
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register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
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register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
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register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
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register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
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#_OFF
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register "off_seq.ops_cnt" = "3"
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register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
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register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
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register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
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device i2c 36 on end
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end
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chip drivers/intel/mipi_camera
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register "acpi_uid" = "3"
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register "acpi_name" = ""VCM0""
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register "chip_name" = ""DW AF VCM""
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register "device_type" = "INTEL_ACPI_CAMERA_VCM"
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register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
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register "vcm_compat" = ""dongwoon,dw9714""
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device i2c 0C on end
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end
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end
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device ref i2c2 on end
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device ref i2c3 on end
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device ref heci1 on end
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device ref sata on end
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device ref i2c5 on
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chip drivers/intel/mipi_camera
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register "acpi_hid" = ""OVTI5675""
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register "acpi_uid" = "0"
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register "acpi_name" = ""CAM1""
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register "chip_name" = ""Ov 5675 Camera""
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register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
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register "ssdb.lanes_used" = "2"
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register "num_freq_entries" = "1"
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register "link_freq[0]" = "450000000"
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register "remote_name" = ""IPU0""
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register "has_power_resource" = "true"
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#Controls
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register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
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register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
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register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
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register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
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#_ON
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register "on_seq.ops_cnt" = "4"
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register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
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register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
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register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
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register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
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#_OFF
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register "off_seq.ops_cnt" = "3"
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register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
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register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
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register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
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device i2c 36 on end
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end
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end
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device ref pcie_rp1 on end
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device ref pcie_rp3 on end # W/A to FSP issue
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device ref pcie_rp4 on end # W/A to FSP issue
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device ref pcie_rp5 on end
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device ref pcie_rp6 on end
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device ref pcie_rp8 on end
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device ref pcie_rp9 on end
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device ref pcie_rp10 on end
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device ref uart0 on end
|
||||
device ref gspi0 on end
|
||||
device ref p2sb on end
|
||||
device pci 1e.3 on
|
||||
chip drivers/spi/acpi
|
||||
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "compat_string" = ""google,cr50""
|
||||
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
|
||||
device spi 0 on end
|
||||
end
|
||||
end # GSPI1
|
||||
device ref hda on
|
||||
chip drivers/intel/soundwire
|
||||
device generic 0 on
|
||||
chip drivers/soundwire/alc711
|
||||
# SoundWire Link 0 ID 1
|
||||
register "desc" = ""Headset Codec""
|
||||
register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1"
|
||||
register "alc711_address.class" = "MIPI_CLASS_NONE"
|
||||
register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711"
|
||||
device generic 0.1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref smbus on end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,403 +0,0 @@
|
|||
chip soc/intel/alderlake
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
register "pmc_gpe0_dw0" = "GPP_B"
|
||||
register "pmc_gpe0_dw1" = "GPP_D"
|
||||
register "pmc_gpe0_dw2" = "GPP_E"
|
||||
|
||||
# FSP configuration
|
||||
|
||||
# Enable CNVi BT
|
||||
register "cnvi_bt_core" = "true"
|
||||
|
||||
# Sagv Configuration
|
||||
register "sagv" = "SaGv_Enabled"
|
||||
|
||||
# Enable DPTF
|
||||
register "dptf_enable" = "true"
|
||||
|
||||
# eMMC HS400
|
||||
register "emmc_enable_hs400_mode" = "true"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # FPS connector
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port2
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port3
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type A/ M.2 WLAN
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port2
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port3
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
|
||||
|
||||
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
|
||||
register "gen1_dec" = "0x00fc0801"
|
||||
register "gen2_dec" = "0x000c0201"
|
||||
# EC memory map range is 0x900-0x9ff
|
||||
register "gen3_dec" = "0x00fc0901"
|
||||
|
||||
# Enable PCH PCIE RP 7 using CLK 3
|
||||
register "pch_pcie_rp[PCH_RP(7)]" = "{
|
||||
.clk_src = 3,
|
||||
.clk_req = 3,
|
||||
.flags = PCIE_RP_CLK_REQ_DETECT,
|
||||
}"
|
||||
|
||||
# Enable PCH PCIE RP 9 using CLK 0
|
||||
register "pch_pcie_rp[PCH_RP(9)]" = "{
|
||||
.clk_src = 0,
|
||||
.clk_req = 0,
|
||||
.flags = PCIE_RP_CLK_REQ_DETECT,
|
||||
}"
|
||||
|
||||
register "sata_salp_support" = "0"
|
||||
|
||||
# Enable EDP in PortA
|
||||
register "ddi_portA_config" = "1"
|
||||
# Enable HDMI in Port B
|
||||
register "ddi_ports_config" = "{
|
||||
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
|
||||
}"
|
||||
|
||||
# TCSS USB3
|
||||
register "tcss_aux_ori" = "4"
|
||||
register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_E20, .pad_auxn_dc = GPP_E21}"
|
||||
|
||||
register "s0ix_enable" = "true"
|
||||
|
||||
register "serial_io_i2c_mode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoPci,
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoPci,
|
||||
}"
|
||||
|
||||
register "serial_io_gspi_mode" = "{
|
||||
[PchSerialIoIndexGSPI0] = PchSerialIoPci,
|
||||
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
register "serial_io_gspi_cs_mode" = "{
|
||||
[PchSerialIoIndexGSPI0] = 0,
|
||||
[PchSerialIoIndexGSPI1] = 0,
|
||||
[PchSerialIoIndexGSPI2] = 0,
|
||||
[PchSerialIoIndexGSPI3] = 0,
|
||||
}"
|
||||
|
||||
register "serial_io_gspi_cs_state" = "{
|
||||
[PchSerialIoIndexGSPI0] = 0,
|
||||
[PchSerialIoIndexGSPI1] = 0,
|
||||
[PchSerialIoIndexGSPI2] = 0,
|
||||
[PchSerialIoIndexGSPI3] = 0,
|
||||
}"
|
||||
|
||||
register "serial_io_uart_mode" = "{
|
||||
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
|
||||
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
|
||||
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
|
||||
}"
|
||||
|
||||
# HD Audio
|
||||
register "pch_hda_dsp_enable" = "1"
|
||||
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
|
||||
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
|
||||
register "pch_hda_idisp_codec_enable" = "1"
|
||||
|
||||
register "cnvi_bt_audio_offload" = "true"
|
||||
|
||||
# Intel Common SoC Config
|
||||
register "common_soc_config" = "{
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[1] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[2] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[3] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
.i2c[5] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
},
|
||||
}"
|
||||
|
||||
# Configure external V1P05/Vnn/VnnSx Rails
|
||||
register "ext_fivr_settings" = "{
|
||||
.configure_ext_fivr = 1,
|
||||
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
|
||||
.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
|
||||
.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
|
||||
.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
|
||||
.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
|
||||
.v1p05_voltage_mv = 1050,
|
||||
.vnn_voltage_mv = 780,
|
||||
.vnn_sx_voltage_mv = 1050,
|
||||
.v1p05_icc_max_ma = 500,
|
||||
.vnn_icc_max_ma = 500,
|
||||
}"
|
||||
|
||||
device domain 0 on
|
||||
device ref igpu on end
|
||||
device ref dtt on
|
||||
chip drivers/intel/dptf
|
||||
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""Ambient""
|
||||
register "options.tsr[1].desc" = ""Battery""
|
||||
register "options.tsr[2].desc" = ""DDR""
|
||||
register "options.tsr[3].desc" = ""Skin""
|
||||
register "options.tsr[4].desc" = ""VR""
|
||||
|
||||
## Active Policy
|
||||
# TODO: below values are initial reference values only
|
||||
register "policies.active" = "{
|
||||
[0] = {
|
||||
.target = DPTF_CPU,
|
||||
.thresholds = {
|
||||
TEMP_PCT(95, 90),
|
||||
TEMP_PCT(90, 80),
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.target = DPTF_TEMP_SENSOR_0,
|
||||
.thresholds = {
|
||||
TEMP_PCT(80, 90),
|
||||
TEMP_PCT(70, 80),
|
||||
}
|
||||
}
|
||||
}"
|
||||
|
||||
## Passive Policy
|
||||
# TODO: below values are initial reference values only
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 95, 10000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 50000),
|
||||
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 50000),
|
||||
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 50000),
|
||||
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 50000),
|
||||
[5] = DPTF_PASSIVE(CPU, TEMP_SENSOR_4, 85, 50000),
|
||||
}"
|
||||
|
||||
## Critical Policy
|
||||
# TODO: below values are initial reference values only
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
|
||||
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
|
||||
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
|
||||
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN),
|
||||
[5] = DPTF_CRITICAL(TEMP_SENSOR_4, 95, SHUTDOWN),
|
||||
}"
|
||||
|
||||
## Power Limits Control
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 3000,
|
||||
.max_power = 15000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 200,
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 25000,
|
||||
.max_power = 35000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 1000,
|
||||
}
|
||||
}"
|
||||
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 3000 },
|
||||
[1] = { 24, 1500 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
|
||||
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||
register "controls.fan_perf" = "{
|
||||
[0] = { 90, 6700, 220, 2200, },
|
||||
[1] = { 80, 5800, 180, 1800, },
|
||||
[2] = { 70, 5000, 145, 1450, },
|
||||
[3] = { 60, 4900, 115, 1150, },
|
||||
[4] = { 50, 3838, 90, 900, },
|
||||
[5] = { 40, 2904, 55, 550, },
|
||||
[6] = { 30, 2337, 30, 300, },
|
||||
[7] = { 20, 1608, 15, 150, },
|
||||
[8] = { 10, 800, 10, 100, },
|
||||
[9] = { 0, 0, 0, 50, }
|
||||
}"
|
||||
|
||||
## Fan options
|
||||
register "options.fan.fine_grained_control" = "true"
|
||||
register "options.fan.step_size" = "2"
|
||||
|
||||
device generic 0 alias dptf_policy on end
|
||||
end
|
||||
end
|
||||
device ref ipu on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "0x50000"
|
||||
register "acpi_name" = ""IPU0""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
|
||||
|
||||
register "cio2_num_ports" = "2"
|
||||
register "cio2_lanes_used" = "{2,2}"
|
||||
register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
|
||||
register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
|
||||
register "cio2_prt[0]" = "2"
|
||||
register "cio2_prt[1]" = "1"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref crashlog off end
|
||||
device ref tcss_xhci on end
|
||||
device ref xhci on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Root Hub""
|
||||
register "type" = "UPC_TYPE_HUB"
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref i2c0 on end
|
||||
device ref i2c1 on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = ""OVTI5675""
|
||||
register "acpi_uid" = "0"
|
||||
register "acpi_name" = ""CAM0""
|
||||
register "chip_name" = ""Ov 5675 Camera""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
|
||||
|
||||
register "ssdb.lanes_used" = "2"
|
||||
register "ssdb.vcm_type" = "0x0C"
|
||||
register "vcm_name" = ""VCM0""
|
||||
register "num_freq_entries" = "1"
|
||||
register "link_freq[0]" = "450000000"
|
||||
register "remote_name" = ""IPU0""
|
||||
|
||||
register "has_power_resource" = "true"
|
||||
#Controls
|
||||
register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
|
||||
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
|
||||
register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "4"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
|
||||
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
|
||||
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
|
||||
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "3"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
|
||||
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 36 on end
|
||||
end
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_uid" = "3"
|
||||
register "acpi_name" = ""VCM0""
|
||||
register "chip_name" = ""DW AF VCM""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
|
||||
|
||||
register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
|
||||
register "vcm_compat" = ""dongwoon,dw9714""
|
||||
|
||||
device i2c 0C on end
|
||||
end
|
||||
end
|
||||
device ref i2c2 on end
|
||||
device ref i2c3 on end
|
||||
device ref heci1 on end
|
||||
device ref sata off end
|
||||
device ref i2c5 on
|
||||
chip drivers/intel/mipi_camera
|
||||
register "acpi_hid" = ""OVTI5675""
|
||||
register "acpi_uid" = "0"
|
||||
register "acpi_name" = ""CAM1""
|
||||
register "chip_name" = ""Ov 5675 Camera""
|
||||
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
|
||||
|
||||
register "ssdb.lanes_used" = "2"
|
||||
register "num_freq_entries" = "1"
|
||||
register "link_freq[0]" = "450000000"
|
||||
register "remote_name" = ""IPU0""
|
||||
|
||||
register "has_power_resource" = "true"
|
||||
#Controls
|
||||
register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
|
||||
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
|
||||
register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
|
||||
register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
|
||||
|
||||
#_ON
|
||||
register "on_seq.ops_cnt" = "4"
|
||||
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
|
||||
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
|
||||
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
|
||||
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
|
||||
|
||||
#_OFF
|
||||
register "off_seq.ops_cnt" = "3"
|
||||
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
|
||||
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
|
||||
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
|
||||
|
||||
device i2c 36 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp7 on end
|
||||
device ref pcie_rp9 on end
|
||||
device ref uart0 on end
|
||||
device ref gspi0 on end
|
||||
device ref p2sb on end
|
||||
device ref emmc on end
|
||||
device ref ish on end
|
||||
device ref ufs on end
|
||||
device ref hda on
|
||||
chip drivers/intel/soundwire
|
||||
device generic 0 on
|
||||
chip drivers/soundwire/alc711
|
||||
# SoundWire Link 0 ID 1
|
||||
register "desc" = ""Headset Codec""
|
||||
register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1"
|
||||
register "alc711_address.class" = "MIPI_CLASS_NONE"
|
||||
register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711"
|
||||
device generic 0.1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref smbus on end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,142 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* WWAN_RST# */
|
||||
PAD_CFG_GPO(GPP_E5, 0, PLTRST),
|
||||
/* WWAN_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_A8, 1, DEEP),
|
||||
|
||||
/* H0 : PCH_SSD_RST# */
|
||||
PAD_CFG_GPO(GPP_H0, 0, PLTRST),
|
||||
/* H13 : CPU_SSD_RST# */
|
||||
PAD_CFG_GPO(GPP_H13, 0, PLTRST),
|
||||
|
||||
/* EC_IN_RW */
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
|
||||
/* CPU PCIe VGPIO for RP0 */
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_10, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_11, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_14, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_15, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_64, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_65, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_66, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_67, NONE, DEEP, NF1),
|
||||
|
||||
/* CPU PCIe vGPIO for RP1 */
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_19, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_22, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_23, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_24, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_25, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_26, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_27, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_28, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_29, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_30, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_31, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_68, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_69, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_70, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_71, NONE, DEEP, NF1),
|
||||
|
||||
/* CPU PCIe vGPIO for RP2 */
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, DEEP, NF1),
|
||||
|
||||
/* CPU PCIe vGPIO for RP3 */
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
|
||||
|
||||
/* H1_PCH_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* TPM */
|
||||
/* F16 : GSPI1_CS0N */
|
||||
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
|
||||
/* F11 : GSPI1_CLK */
|
||||
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
|
||||
/* F13 : GSPI1_MISO */
|
||||
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
|
||||
/* F12 : GSPI1_MOSI */
|
||||
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
|
||||
|
||||
/* D10 : PCH_SSD_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_D10, 1, PLTRST),
|
||||
/* D16 : CPU_SSD_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
|
||||
|
||||
};
|
||||
|
||||
static const struct pad_config early_uart_gpio_table[] = {
|
||||
/* UART0 RX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* UART0 TX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
};
|
||||
|
||||
void variant_configure_early_gpio_pads(void)
|
||||
{
|
||||
if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
|
||||
gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
|
||||
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* WWAN_RST# */
|
||||
PAD_CFG_GPO(GPP_F14, 0, PLTRST),
|
||||
/* WWAN_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_D17, 1, DEEP),
|
||||
/* EC_IN_RW */
|
||||
PAD_CFG_GPI(GPP_E7, NONE, DEEP),
|
||||
};
|
||||
|
||||
static const struct pad_config early_uart_gpio_table[] = {
|
||||
/* UART0 RX */
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
|
||||
/* UART0 TX */
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
|
||||
};
|
||||
|
||||
void variant_configure_early_gpio_pads(void)
|
||||
{
|
||||
if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
|
||||
gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
|
||||
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
|
|
@ -1,193 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
/* Pad configuration in ramstage */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* A12 : BT_RF_KILL_N */
|
||||
PAD_CFG_GPO(GPP_A12, 1, PLTRST),
|
||||
|
||||
/* H2 : WLAN_RST_N */
|
||||
PAD_CFG_GPO(GPP_H2, 1, PLTRST),
|
||||
/* 8 : M.2_BTWIFI_SUS_CLK */
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* 9 : GPD_9_SLP_WLAN_N */
|
||||
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
/* 10 : GPD_10_SLP_S5_N */
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
|
||||
/* D12 : WIFI_RF_KILL_N */
|
||||
PAD_CFG_GPO(GPP_D12, 1, PLTRST),
|
||||
/* D13 : WIFI_WAKE_N */
|
||||
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
|
||||
/* D14 : x1 PCIE slot1 PWREN / SML0B_CLK */
|
||||
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
|
||||
/* D15 : WWAN_DISABLE_N */
|
||||
PAD_CFG_GPO(GPP_D15, 1, PLTRST),
|
||||
/* D17 : PCIE SLOT1 WAKE N */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_D17, NONE, DEEP, LEVEL, INVERT),
|
||||
/* D18 : WWAN WAKE N*/
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
|
||||
/* H23 : CLKREQ5_WWAN_N */
|
||||
PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
|
||||
|
||||
/* F0 : CNV_BRI_DT_BT_UART2_RTS_N */
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
/* F1 : CNV_BRI_RSP_BT_UART2_RXD */
|
||||
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
|
||||
/* F2 : CNV_RGI_DT_BT_UART2_TXD */
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
/* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */
|
||||
PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
|
||||
/* F4 : CNV_RF_RESET_R_N */
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
/* F5 : MODEM_CLKREQ_R */
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
/* F6 : GPPC_F6_CNV_PA_BLANKING */
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
/* F10 : GPPC_F10 X1_Slot_RESET */
|
||||
PAD_CFG_GPO(GPP_F10, 1, PLTRST),
|
||||
/* H8 : CNV_MFUART2_RXD */
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
|
||||
/* H9 : CNV_MFUART2_TXD */
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
|
||||
|
||||
/* A14 : TCPC01_TYPEA23_OC1_N */
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
/* A15 : USB_TYPEA_OC2_N */
|
||||
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
|
||||
/* E18 : TBT_LSX0_TXD */
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
|
||||
/* E19 : TBT_LSX0_RXD */
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
|
||||
/* E20 : TBT_LSX1_TXD */
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
|
||||
/* E21 : TBT_LSX1_RXD */
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
|
||||
|
||||
/* H4 : I2C0 SDA */
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
/* H6 : I2C1 SDA */
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
/* B16 : I2C5 SDA */
|
||||
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
|
||||
|
||||
/* H5 : I2C0 SCL */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
/* H7 : I2C1 SCL */
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
/* B17 : I2C5 SCL */
|
||||
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
|
||||
|
||||
/* C5 : WWAN_PERST_N */
|
||||
PAD_CFG_GPO(GPP_C5, 1, PLTRST),
|
||||
/* E5 : WWAN_PERST# */
|
||||
PAD_CFG_GPO(GPP_E5, 1, PLTRST),
|
||||
/* D15 : WWAN_DISABLE_N */
|
||||
PAD_CFG_GPO(GPP_D15, 1, PLTRST),
|
||||
/* D9 : WWAN_FCP_POWER_OFF_N */
|
||||
PAD_CFG_GPO(GPP_D9, 1, PLTRST),
|
||||
|
||||
/* H0 : PCH_SSD_RST# */
|
||||
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
|
||||
/* H13 : CPU_SSD_RST# */
|
||||
PAD_CFG_GPO(GPP_H13, 1, PLTRST),
|
||||
|
||||
/* DDP1/2/A/B CTRLCLK and CTRLDATA pins */
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
|
||||
PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
|
||||
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
|
||||
PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_E23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
|
||||
/* HPD_1 (E14) and HPD_2 (A18) pins */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
|
||||
/* GPIO pin for PCIE SRCCLKREQB */
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
|
||||
|
||||
/* CAM1_RST */
|
||||
PAD_CFG_GPO(GPP_R5, 1, PLTRST),
|
||||
/* CAM2_RST */
|
||||
PAD_CFG_GPO(GPP_E15, 1, PLTRST),
|
||||
/* CAM1_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_B23, 1, PLTRST),
|
||||
/* CAM2_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_E16, 1, PLTRST),
|
||||
/* IMGCLKOUT0 */
|
||||
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
|
||||
/* IMGCLKOUT1 */
|
||||
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
|
||||
|
||||
/* C16 : I2C0 SDA */
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
|
||||
/* S0 : SNDW1_CLK */
|
||||
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
|
||||
|
||||
/* S1 : SNDW1_DATA */
|
||||
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
|
||||
|
||||
/* S2 : SNDW2_CLK */
|
||||
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
|
||||
|
||||
/* S3 : SNDW2_DATA */
|
||||
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
|
||||
|
||||
/* S4 : SNDW3_CLK */
|
||||
PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
|
||||
|
||||
/* S5 : SNDW3_DATA */
|
||||
PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
|
||||
|
||||
/* S6 : SNDW4_CLK */
|
||||
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
|
||||
|
||||
/* S7 : SNDW4_DATA */
|
||||
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
|
||||
|
||||
/* F7 : TCH_PNL_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_F7, 1, PLTRST),
|
||||
/* F17 : RST_N_TCH_PNL2 */
|
||||
PAD_CFG_GPO(GPP_F17, 1, PLTRST),
|
||||
/* F18 : INT_N_TCH_PNL2 */
|
||||
PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE),
|
||||
|
||||
/* E3 : H1_PCH_INT_ODL */
|
||||
PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
|
||||
|
||||
/* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
|
||||
PAD_CFG_GPO(GPP_E4, 0, DEEP),
|
||||
|
||||
/* H1 : GPPC_H1_TCH_PAD_TCH_PNL2_LS_EN */
|
||||
PAD_CFG_GPO(GPP_H1, 0, PLTRST),
|
||||
|
||||
/* D11 : TCH_PAD_INT_N */
|
||||
PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST, LEVEL, INVERT)
|
||||
};
|
||||
|
||||
void variant_configure_gpio_pads(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
DECLARE_CROS_GPIOS(cros_gpios);
|
||||
|
|
@ -1,239 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
/* Pad configuration in ramstage*/
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* ESPI_IO0_EC_R / ESPI_IO0_HDR */
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
/* ESPI_IO1_EC_R / ESPI_IO1_HDR */
|
||||
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
|
||||
/* ESPI_IO2_EC_R / ESPI_IO2_HDR */
|
||||
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
|
||||
/* ESPI_IO3_EC_R / ESPI_IO3_HDR */
|
||||
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
|
||||
/* ESPI_CS0_EC_R_N / ESPI_CS0_HDR_N */
|
||||
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
|
||||
/* ESPI_ALERT0_EC_R_N / ESPI_ALERT0_HDR_N */
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
/* ESPI_CLK_EC_R / ESPI_CLK_HDR */
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||
/* ESPI_RST_EC_R_N / ESPI_RST_HDR_N */
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
|
||||
|
||||
/* EC_SLP_S0_CS_N */
|
||||
PAD_CFG_GPO(GPP_E4, 1, PLTRST),
|
||||
|
||||
/* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */
|
||||
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
|
||||
/* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
|
||||
/* M.2_SSD_PDET_R */
|
||||
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
|
||||
/* CLKREQ0_M2_SSD_N */
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
/* M2_PCH_SSD_PWREN */
|
||||
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
|
||||
/* M2_SSD_RST_N */
|
||||
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
|
||||
/* M2_SSD_DEVSLP */
|
||||
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
|
||||
|
||||
/* I5 : NC */
|
||||
PAD_NC(GPP_I5, NONE),
|
||||
/* I7 : EMMC_CMD ==> EMMC_CMD */
|
||||
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
|
||||
/* I8 : EMMC_DATA0 ==> EMMC_D0 */
|
||||
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
|
||||
/* I9 : EMMC_DATA1 ==> EMMC_D1 */
|
||||
PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
|
||||
/* I10 : EMMC_DATA2 ==> EMMC_D2 */
|
||||
PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
|
||||
/* I11 : EMMC_DATA3 ==> EMMC_D3 */
|
||||
PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1),
|
||||
/* I12 : EMMC_DATA4 ==> EMMC_D4 */
|
||||
PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1),
|
||||
/* I13 : EMMC_DATA5 ==> EMMC_D5 */
|
||||
PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1),
|
||||
/* I14 : EMMC_DATA6 ==> EMMC_D6 */
|
||||
PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1),
|
||||
/* I15 : EMMC_DATA7 ==> EMMC_D7 */
|
||||
PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1),
|
||||
/* I16 : EMMC_RCLK ==> EMMC_RCLK */
|
||||
PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1),
|
||||
/* I17 : EMMC_CLK ==> EMMC_CLK */
|
||||
PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1),
|
||||
/* I18 : EMMC_RESET# ==> EMMC_RST_L */
|
||||
PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1),
|
||||
|
||||
/* TYPEA_CONN23_USB2_P8_OC1_N */
|
||||
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
|
||||
/* CRD1_PWREN */
|
||||
PAD_CFG_GPO(GPP_B23, 1, PLTRST),
|
||||
/* TCP1_DISP_AUX_P_BIAS_GPIO */
|
||||
PAD_CFG_GPO(GPP_E20, 1, PLTRST),
|
||||
/* TCP1_DISP_AUX_N_BIAS_GPIO */
|
||||
PAD_CFG_GPO(GPP_E21, 0, PLTRST),
|
||||
/* TCP0_DISP_AUX_P_BIAS_GPIO */
|
||||
PAD_CFG_GPO(GPP_E22, 0, PLTRST),
|
||||
/* TCP0_DISP_AUX_N_BIAS_GPIO */
|
||||
PAD_CFG_GPO(GPP_E23, 1, PLTRST),
|
||||
|
||||
/* EDP1_HPD_MIPI_PNL_RST */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
|
||||
/* X1_SLOT_PWREN */
|
||||
PAD_CFG_GPO(GPP_A8, 0, PLTRST),
|
||||
/* SML0_CLK */
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
/* SML0_DATA */
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
/* CLKREQ3_X1PCIE_SLOT_N */
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
/* X1_PCIE_SLOT_WAKE_N */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_D11, NONE, DEEP, LEVEL, INVERT),
|
||||
/* X1_Slot_RESET */
|
||||
PAD_CFG_GPO(GPP_F10, 1, PLTRST),
|
||||
|
||||
/* WWAN_PERST_N */
|
||||
PAD_CFG_GPO(GPP_C5, 1, PLTRST),
|
||||
/* CLKREQ1_WWAN_N */
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
/* GPPC_D15_M.2_WWAN_DISABLE_N */
|
||||
PAD_CFG_GPO(GPP_D15, 1, PLTRST),
|
||||
/* WWAN_PWREN */
|
||||
PAD_CFG_GPO(GPP_D17, 1, PLTRST),
|
||||
/* WWAN WAKE N */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), //TODO SCI
|
||||
/* SRCCLK_OEB6 */
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF3),
|
||||
/* GPPC_F6_CNV_PA_BLANKING */
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
/* WWAN_RST# */
|
||||
PAD_CFG_GPO(GPP_F14, 1, PLTRST),
|
||||
/* WWAN_FCP_OFF_N */
|
||||
PAD_CFG_GPO(GPP_F15, 1, PLTRST),
|
||||
/* CNV_MFUART2_RXD */
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
|
||||
/* CNV_MFUART2_RXD */
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
|
||||
|
||||
/* PM_SLP_S0_N */
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
/* PLT_RST_N */
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
/* PM_SLP_DRAM_N */
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2),
|
||||
/* CPU_C10_GATE_N_R */
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
|
||||
/* CODEC_INT_N */
|
||||
PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT),
|
||||
/* SNDW0_CLK_HDR */
|
||||
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
|
||||
/* SNDW0_DATA_HDR */
|
||||
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
|
||||
/* SNDW1_CLK_DMIC_CLK_A_0 */
|
||||
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
|
||||
/* SNDW1_DATA_DMIC_DATA_0 */
|
||||
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
|
||||
/* SNDW2_CLK_R */
|
||||
PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
|
||||
/* SNDW2_DATA_R */
|
||||
PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
|
||||
/* SOC_DMIC0_SNDW3_CLK */
|
||||
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
|
||||
/* SOC_DMIC0_SNDW3_DATA */
|
||||
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
|
||||
|
||||
/* I2C_SCL(0) */
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
/* I2C_SDA(0) */
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
|
||||
/* DDIB_DP_HDMI_ALS_HDP */
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
|
||||
/* 8 : M.2_BTWIFI_SUS_CLK */
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
/* 9 : GPD_9_SLP_WLAN_N */
|
||||
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
|
||||
/* SRCCLK_OEB7 */
|
||||
PAD_CFG_GPO(GPP_A7, 0, PLTRST),
|
||||
|
||||
/* GPIO pin for PCIE SRCCLKREQB_2 */
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
|
||||
/* H2 : WLAN_RST_N */
|
||||
PAD_CFG_GPO(GPP_H2, 1, PLTRST),
|
||||
/* I2C_SDA(1) */
|
||||
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
|
||||
/* I2C_SCL(1) */
|
||||
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
|
||||
|
||||
/* CAM_PRIVACY_LED */
|
||||
PAD_CFG_GPO(GPP_B14, 1, PLTRST),
|
||||
|
||||
/* B16 : I2C5 SDA */
|
||||
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
|
||||
/* B17 : I2C5 SCL */
|
||||
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
|
||||
|
||||
/* CAM_STROBE */
|
||||
PAD_CFG_GPO(GPP_B18, 0, PLTRST),
|
||||
/* CAM1_RST_N */
|
||||
PAD_CFG_GPO(GPP_A21, 1, PLTRST),
|
||||
/* CAM1_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_B23, 1, PLTRST),
|
||||
/* CAM2_RST */
|
||||
PAD_CFG_GPO(GPP_E15, 1, PLTRST),
|
||||
/* CAM2_PWR_EN */
|
||||
PAD_CFG_GPO(GPP_E16, 1, PLTRST),
|
||||
|
||||
/* IMGCLKOUT */
|
||||
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
|
||||
|
||||
/* BT_RF_KILL_N */
|
||||
PAD_CFG_GPO(GPP_A13, 1, PLTRST),
|
||||
|
||||
/* D13 : WIFI_WAKE_N */
|
||||
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
|
||||
/* WIFI RF KILL */
|
||||
PAD_CFG_GPO(GPP_E3, 1, PLTRST),
|
||||
|
||||
/* F0 : CNV_BRI_DT_BT_UART2_RTS_N */
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
/* F1 : CNV_BRI_RSP_BT_UART2_RXD */
|
||||
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
|
||||
/* F2 : CNV_RGI_DT_BT_UART2_TXD */
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
/* F3 : CNV_RGI_RSP_BT_UART2_CTS_N */
|
||||
PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
|
||||
/* F4 : CNV_RF_RESET_R_N */
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
|
||||
/* F5 : MODEM_CLKREQ_R */
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
|
||||
/* TCH PAD Power EN */
|
||||
PAD_CFG_GPO(GPP_F7, 1, PLTRST),
|
||||
|
||||
/* UART_BT_WAKE_N */
|
||||
PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT),
|
||||
};
|
||||
|
||||
void variant_configure_gpio_pads(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
||||
static const struct cros_gpio cros_gpios[] = {
|
||||
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
|
||||
};
|
||||
DECLARE_CROS_GPIOS(cros_gpios);
|
||||
Loading…
Add table
Add a link
Reference in a new issue