mb/siemens/mc_rpl: Remove Chrome OS and EC as they are not used
This mainboard neither uses Chrome OS nor has any embedded controller available. This patch removes all references from the build in this regard. This also requires some refactoring in board_id.c. Change-Id: If834480fbdac4b4843c265a257d3a77678f56aab Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87666 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Werner Zeh
Matt DeVillier
parent
e020979993
commit
8fdf8694e3
7 changed files with 3 additions and 149 deletions
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@ -16,52 +16,26 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_SPD_IN_CBFS
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select MAINBOARD_HAS_CHROMEOS
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select SOC_INTEL_COMMON_BLOCK_IPU
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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select SOC_INTEL_CSE_LITE_SKU
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config BOARD_SIEMENS_MC_RPL1
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select BOARD_SIEMENS_BASEBOARD_MC_RPL
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select DRIVERS_UART_8250IO
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select GEN3_EXTERNAL_CLOCK_BUFFER
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select MAINBOARD_USES_IFD_EC_REGION
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select SOC_INTEL_ALDERLAKE_PCH_P
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select SOC_INTEL_RAPTORLAKE
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if BOARD_SIEMENS_BASEBOARD_MC_RPL
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config SOC_INTEL_CSE_LITE_SKU
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bool "Use CSE Lite firmware"
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default y if MC_RPL_CHROME_EC
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help
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Enable if CSE Lite firmware is used in your build. It is commonly
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used in Chrome boards (chromebooks, chromeboxes, ...).
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But since ADL RVP build can be used with or without CSE Lite firmware
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it is a configurable option. Alderlake RVP boards usually don't use
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an CSE Lite firmware, but are still very likely to use it in case
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ChromeEC is used.
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config CHROMEOS
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select GBB_FLAG_FORCE_DEV_SWITCH_ON
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select GBB_FLAG_FORCE_DEV_BOOT_USB
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select GBB_FLAG_FORCE_DEV_BOOT_ALTFW
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select GBB_FLAG_FORCE_MANUAL_RECOVERY
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select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
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select HAS_RECOVERY_MRC_CACHE
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config MAINBOARD_DIR
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default "siemens/mc_rpl"
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config VARIANT_DIR
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default "mc_rpl1" if BOARD_SIEMENS_MC_RPL1
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config GBB_HWID
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string
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depends on CHROMEOS
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default "ADLRVPN TEST 7673" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC
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default "ADLRVPP TEST 2418"
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config MAINBOARD_PART_NUMBER
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default "MC RPL1" if BOARD_SIEMENS_MC_RPL1
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@ -82,32 +56,6 @@ config OVERRIDE_DEVICETREE
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_rpl.fmd"
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choice
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prompt "ON BOARD EC"
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default MC_RPL_CHROME_EC if BOARD_SIEMENS_MC_RPL1
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help
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This option allows you to select the on board EC to use.
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Select whether the board has Intel EC or Chrome EC
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config MC_RPL_CHROME_EC
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bool "Chrome EC"
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_ESPI
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_ACPI
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select EC_GOOGLE_CHROMEEC_LPC
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config MC_RPL_INTEL_EC
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bool "Intel EC"
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select EC_ACPI
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endchoice
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config VBOOT
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select VBOOT_LID_SWITCH
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select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC
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select EC_GOOGLE_CHROMEEC_SWITCHES if MC_RPL_CHROME_EC
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select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_N_EXT_EC
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config UART_FOR_CONSOLE
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int
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default 0
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@ -118,10 +66,6 @@ config DRIVER_TPM_SPI_BUS
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config USE_PM_ACPI_TIMER
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default n if BOARD_SIEMENS_MC_RPL1
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 67 if BOARD_INTEL_ADLRVP_RPL_EXT_EC # GPE0_DW2_3 (GPP_E3)
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config GEN3_EXTERNAL_CLOCK_BUFFER
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bool
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depends on SOC_INTEL_ALDERLAKE_PCH_P
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@ -3,7 +3,6 @@
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subdirs-y += spd
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bootblock-y += bootblock.c
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bootblock-$(CONFIG_CHROMEOS) += chromeos.c
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ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
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bootblock-y += early_gpio_n.c
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ramstage-y += gpio_n.c
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@ -12,9 +11,6 @@ bootblock-y += early_gpio.c
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ramstage-y += gpio.c
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endif
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-y += romstage_fsp_params.c
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romstage-y += board_id.c
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romstage-y += memory.c
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@ -22,8 +18,6 @@ ifeq ($(CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC),y)
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romstage-y += memory_rpl.c
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endif
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-y += ec.c
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ramstage-y += mainboard.c
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ramstage-y += board_id.c
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ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
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@ -1,15 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <boardid.h>
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#include <ec/acpi/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <types.h>
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#include "board_id.h"
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/* Get Board ID via EC I/O port write/read */
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/* Get Board ID */
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int get_board_id(void)
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{
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static int id = 1;
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return (id & BOARD_ID_MASK);
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return 1;
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}
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@ -3,11 +3,6 @@
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#ifndef _MAINBOARD_COMMON_BOARD_ID_H_
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#define _MAINBOARD_COMMON_BOARD_ID_H_
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/* Board/FAB ID Command */
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#define EC_FAB_ID_CMD 0x0d
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/* Bit 5:0 for Board ID */
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#define BOARD_ID_MASK 0x3f
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/*
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* Returns board information (board id[15:8] and
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* Fab info[7:0]) on success and < 0 on error
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@ -1,50 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/gpio.h>
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#include <bootmode.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <types.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
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};
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if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) ||
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CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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else
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios) - 1);
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}
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#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES)
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int get_lid_switch(void)
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{
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/* Lid always open */
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return 1;
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}
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int get_recovery_mode_switch(void)
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{
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return 0;
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}
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#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
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int get_write_protect_state(void)
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{
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/* No write protect */
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return 0;
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}
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#if (CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC) ||\
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CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC))
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int get_ec_is_trusted(void)
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{
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/* EC is trusted if not in RW. */
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return !gpio_get(GPIO_EC_IN_RW);
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}
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#endif
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@ -41,12 +41,6 @@ chip soc/intel/alderlake
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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# Enable PCH PCIE RP 5 using CLK 2
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register "pch_pcie_rp[PCH_RP(5)]" = "{
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.clk_src = 2,
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@ -1,19 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <baseboard/ec.h>
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void mainboard_ec_init(void)
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{
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const struct google_chromeec_event_info info = {
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.log_events = MAINBOARD_EC_LOG_EVENTS,
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.sci_events = MAINBOARD_EC_SCI_EVENTS,
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.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
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.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
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.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
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};
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google_chromeec_events_init(&info, acpi_is_wakeup_s3());
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}
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