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mb/google/fatcat/var/kinmen: Update GPIO table

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Configure GPIOs and related settings per schematic_20250520_v25.

BUG=b:409148565
TEST=emerge-fatcat coreboot

Change-Id: Ib18560de601b98f3b8f45adab5d81686ea236ac9
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Ivy Jian 2025-05-21 09:44:48 +08:00 • committed by Matt DeVillier
commit bbcb222f0b
3 changed files with 223 additions and 188 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/mainboard/google/fatcat/Kconfig
View file

@ -93,6 +93,7 @@ config BOARD_GOOGLE_FRANCKA
config BOARD_GOOGLE_KINMEN
select BOARD_GOOGLE_BASEBOARD_FATCAT
select HAVE_SLP_S0_GATE
if BOARD_GOOGLE_FATCAT_COMMON
@ -161,7 +162,7 @@ config TPM_TIS_ACPI_INTERRUPT
default 47 if BOARD_GOOGLE_MODEL_FATCAT # GPE0_DW1_15 (GPP_D15)
default 79 if BOARD_GOOGLE_FELINO # GPE0_DW2_15 (GPP_F15)
default 11 if BOARD_GOOGLE_FRANCKA # GPE0_DW0_11 (GPP_H11)
default 47 if BOARD_GOOGLE_KINMEN # GPE0_DW1_15 (GPP_D15)
default 66 if BOARD_GOOGLE_KINMEN # GPE0_DW2_02 (GPP_E02)
# FIXME: update as per board schematics
config UART_FOR_CONSOLE

3
src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
View file

@ -33,7 +33,8 @@
#elif CONFIG(BOARD_GOOGLE_KINMEN)
#define EC_SYNC_IRQ GPP_E07_IRQ
#define GPIO_PCH_WP GPP_D02
#define GPIO_SLP_S0_GATE 0 /* Not Connected */
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_V17
#endif
#endif /* __BASEBOARD_GPIO_H__ */

405
src/mainboard/google/fatcat/variants/kinmen/gpio.c
View file

@ -28,18 +28,20 @@ static const struct pad_config gpio_table[] = {
/* GPP_A06: ESPI_RST_EC_R_N */
/* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
/* GPP_A09: M.2_WWAN_FCP_OFF_N */
PAD_CFG_GPO(GPP_A09, 1, PLTRST),
/* GPP_A10: M.2_WWAN_DISABLE_N */
PAD_CFG_GPO(GPP_A10, 1, PLTRST),
/* GPP_A11: WLAN_RST_N */
PAD_CFG_GPO(GPP_A11, 1, PLTRST),
/* GPP_A12: WIFI_WAKE_N */
PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
/* GPP_A08: NC */
PAD_NC(GPP_A08, NONE),
/* GPP_A09: NC */
PAD_NC(GPP_A09, NONE),
/* GPP_A10: NC */
PAD_NC(GPP_A10, NONE),
/* GPP_A11: NC */
PAD_NC(GPP_A11, NONE),
/* GPP_A12: NC */
PAD_NC(GPP_A12, NONE),
/* GPP_A13: MEM_STRAP_0 */
PAD_CFG_GPI(GPP_A13, NONE, DEEP),
/* GPP_A15: GPP_A15_DNX_FORCE_RELOAD */
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
/* GPP_A15: NC */
PAD_NC(GPP_A15, NONE),
/* GPP_A16: BT_RF_KILL_N */
PAD_CFG_GPO(GPP_A16, 1, DEEP),
/* GPP_A17: WIFI_RF_KILL_N */
@ -49,39 +51,37 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
/* GPP_B01: USBC_SML_DATA_PD */
PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
/* GPP_B02: ISH_I2C0_SDA_SNSR_HDR */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
/* GPP_B03: ISH_I2C0_SCL_SNSR_HDR */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
/* GPP_B04: ISH_GP_0_SNSR_HDR */
PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
/* GPP_B02: NC */
PAD_NC(GPP_B02, NONE),
/* GPP_B03: NC */
PAD_NC(GPP_B03, NONE),
/* GPP_B04: NC */
PAD_NC(GPP_B04, NONE),
/* GPP_B05: ISH_GP_1_SNSR_HDR */
PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
/* GPP_B06: ISH_GP_2_SNSR_HDR */
PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
/* GPP_B07: ISH_GP_3_SNSR_HDR */
PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
/* GPP_B08: ISH_GP_4_SNSR_HDR */
PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
/* GPP_B09: M2_GEN4_SSD_RESET_N */
PAD_CFG_GPO(GPP_B09, 1, PLTRST),
/* GPP_B10: GEN4_SSD_PWREN */
PAD_CFG_GPO(GPP_B10, 1, PLTRST),
/* GPP_B11: MOD_TCSS1_DISP_HPD3 */
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
/* GPP_B06: NC */
PAD_NC(GPP_B06, NONE),
/* GPP_B07: NC */
PAD_NC(GPP_B07, NONE),
/* GPP_B08: NC */
PAD_NC(GPP_B08, NONE),
/* GPP_B09: NC */
PAD_NC(GPP_B09, NONE),
/* GPP_B10: NC */
PAD_NC(GPP_B10, NONE),
/* GPP_B11: USB_OC1 */
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
/* GPP_B12: PM_SLP_S0_N */
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* GPP_B13: PLT_RST_N */
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* GPP_B14: MOD_TCSS2_DISP_HPD4 */
/* GPP_B14: DISP_HPD4 */
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
/* GPP_B15: MOD_TCSS_USB_TYP_A_OC3_N */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* GPP_B15: NC */
PAD_NC(GPP_B15, NONE),
/* GPP_B16: GEN5_SSD_PWREN */
PAD_CFG_GPO(GPP_B16, 1, PLTRST),
/* GPP_B17: Not used */
/* GPP_B17: NC */
PAD_NC(GPP_B17, NONE),
/* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
@ -89,78 +89,86 @@ static const struct pad_config gpio_table[] = {
/* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
/* GPP_B20: M.2_WWAN_RST_N */
PAD_CFG_GPO(GPP_B20, 1, PLTRST),
/* GPP_B20: NC */
PAD_NC(GPP_B20, NONE),
/* GPP_B21: TCP_RETIMER_FORCE_PWR */
PAD_CFG_GPO(GPP_B21, 0, DEEP),
/* GPP_B22: ISH_GP_5_SNSR_HDR */
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
/* GPP_B23: ISH_GP_6_SNSR_HDR */
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
/* GPP_B23: NC */
PAD_NC(GPP_B23, NONE),
/* GPP_B24: MEM_STRAP_3 */
PAD_CFG_GPI(GPP_B24, NONE, DEEP),
/* GPP_B25: MEM_STRAP_2 */
PAD_CFG_GPI(GPP_B25, NONE, DEEP),
/* GPP_C00: GPP_C0_SMBCLK */
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
/* GPP_C01: GPP_C1_SMBDATA */
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
/* GPP_C02: Not used */
/* GPP_C00: NC */
PAD_NC(GPP_C00, NONE),
/* GPP_C01: NC */
PAD_NC(GPP_C01, NONE),
/* GPP_C02: NC */
PAD_NC(GPP_C02, NONE),
/* GPP_C03: TCP_LAN_SML0_SCL_R */
PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
/* GPP_C04: TCP_LAN_SML0_SDA_R */
PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
/* GPP_C06: SML1_CLK */
PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
/* GPP_C03: NC */
PAD_NC(GPP_C03, NONE),
/* GPP_C04: NC */
PAD_NC(GPP_C04, NONE),
/* GPP_C05: NC */
PAD_NC(GPP_C05, NONE),
/* GPP_C06: EN_FCAM_PWR */
PAD_CFG_GPO(GPP_C06, 1, DEEP),
/* GPP_C07: MEM_CH_SEL */
PAD_CFG_GPI(GPP_C07, NONE, DEEP),
/* GPP_C09: CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */
PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
/* GPP_C08: NC */
PAD_NC(GPP_C08, NONE),
/* GPP_C09: NC */
PAD_NC(GPP_C09, NONE),
/* GPP_C10: CLKREQ1_X4_GEN5_M2_SSD_N */
PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
/* GPP_C11: CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
/* GPP_C12: CLKREQ3_X1_GEN1_GBE_LAN_N */
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
/* GPP_C11: NC */
PAD_NC(GPP_C11, NONE),
/* GPP_C12: NC */
PAD_NC(GPP_C12, NONE),
/* GPP_C13: CLKREQ4_X1_GEN4_M2_WLAN_N */
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
/* GPP_C14: CLKREQ5_X1_GEN4_M2_WWAN_N */
PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
/* GPP_C14: NC */
PAD_NC(GPP_C14, NONE),
/* GPP_C15: FPS_RST_N */
PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG),
/* GPP_C16: TBT_LSX0_TXD */
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
/* GPP_C17: TBT_LSX0_RXD */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
/* GPP_C18: TBT_LSX1_TXD */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
/* GPP_C19: TBT_LSX1_RXD */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
/* GPP_C20: MOD_TCSS1_LS_TX_DDC_SCL */
/* GPP_C18: NC */
PAD_NC(GPP_C18, NONE),
/* GPP_C19: NC */
PAD_NC(GPP_C19, NONE),
/* GPP_C20: TBT_LSX2_TXD */
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
/* GPP_C21: MOD_TCSS1_LS_RX_DDC_SDA */
/* GPP_C21: TBT_LSX2_RXD */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
/* GPP_C22: MOD_TCSS2_LS_TX_DDC_SCL */
/* GPP_C22: DDP3_CTRLCLK */
PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
/* GPP_C23: MOD_TCSS2_LS_RX_DDC_SDA */
/* GPP_C23: DDP3_CTRLDATA */
PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
/* GPP_D00: IMGCLKOUT_1 */
PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
/* GPP_D02: Not used */
PAD_NC(GPP_D02, NONE),
/* GPP_D03: M.2_WWAN_PERST_GPIO_N */
PAD_CFG_GPO(GPP_D03, 1, PLTRST),
/* GPP_D04: IMGCLKOUT_0 */
PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
/* GPP_D00: NC */
PAD_NC(GPP_D00, NONE),
/* GPP_D01: NC */
PAD_NC(GPP_D01, NONE),
/* GPP_D02: SOC_WP_OD */
PAD_CFG_GPI(GPP_D02, NONE, DEEP),
/* GPP_D03: NC */
PAD_NC(GPP_D03, NONE),
/* GPP_D04: NC */
PAD_NC(GPP_D04, NONE),
/* GPP_D05: disable ISH_UART0_RXD */
PAD_NC(GPP_D05, NONE),
/* GPP_D07: NC */
PAD_NC(GPP_D07, NONE),
/* GPP_D08: NC */
PAD_NC(GPP_D08, NONE),
/* GPP_D09: PEG_SLOT_RST_N */
PAD_CFG_GPO(GPP_D09, 1, PLTRST),
/* GPP_D09: I2S_MCLK1_OUT */
PAD_CFG_NF(GPP_D09, NONE, DEEP, NF2),
/* GPP_D10: HDA_BCLK */
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
/* GPP_D11: HDA_SYNC */
@ -169,64 +177,73 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
/* GPP_D13: HDA_SDI0 */
PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
/* GPP_D14: COINLESS_MODE_SELECT */
PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, LEVEL, ACPI),
/* GPP_D15: SPI_TPM_INT_N */
PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_D16: HDA_RST_N_HDR */
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
/* GPP_D17: HDA_SDI1_HDR */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* GPP_D18: CLKREQ6_X4_GEN4_M2_SSD_N */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
/* GPP_D14: NC */
PAD_NC(GPP_D14, NONE),
/* GPP_D15: NC */
PAD_NC(GPP_D15, NONE),
/* GPP_D16: DMIC_CLK */
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
/* GPP_D17: DMIC_DATA */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
/* GPP_D18: NC */
PAD_NC(GPP_D18, NONE),
/* GPP_D19: NC */
PAD_NC(GPP_D19, NONE),
/* GPP_D20: CSE_EARLY_SW */
PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
/* GPP_D21: NC */
PAD_NC(GPP_D21, NONE),
/* GPP_D22: BPKI3C_SDA */
PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
/* GPP_D23: BPKI3C_SCL */
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
/* GPP_D22: NC */
PAD_NC(GPP_D22, NONE),
/* GPP_D23: NC */
PAD_NC(GPP_D23, NONE),
/* GPP_D24: MEM_STRAP_1 */
PAD_CFG_GPI(GPP_D24, NONE, DEEP),
/* GPP_D25: X4_SLOT_WAKE_N */
PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),
/* GPP_D25: NC */
PAD_NC(GPP_D25, NONE),
/* GPP_E01: CRD2_RST_N */
PAD_CFG_GPO(GPP_E01, 1, PLTRST),
/* GPP_E02: WWAN_WAKE_GPIO_N */
PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
/* GPP_E03: M2_GEN5_SSD_RESET_N */
/* GPP_E01: NC */
PAD_NC(GPP_E01, NONE),
/* GPP_E02: GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC_LOCK(GPP_E02, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_E03: GEN5_SSD_RESET_N */
PAD_CFG_GPO(GPP_E03, 1, PLTRST),
/* GPP_E06: SECURE_CAM_SW */
PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
/* GPP_E05: TCHSCR_RPT_EN */
PAD_CFG_GPO(GPP_E05, 0, PLTRST),
/* GPP_E06: NC */
PAD_NC(GPP_E06, NONE),
/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_E08: Not used */
/* GPP_E08: NC */
PAD_NC(GPP_E08, NONE),
/* GPP_E09: USB_RD_FP_CONN_12_OC0_N */
/* GPP_E09: USB_OC0 */
PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
/* GPP_E10: CRD1_RST_N */
PAD_CFG_GPO(GPP_E10, 1, PLTRST),
/* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
/* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 */
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
/* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
/* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
/* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */
PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
/* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */
/* THC NOTE: use GPO instead of GPO for THC0 Rst */
PAD_CFG_GPO(GPP_E16, 1, DEEP),
/* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
/* GPP_E10: NC */
PAD_NC(GPP_E10, NONE),
/* GPP_E11: GPSI0_CLK */
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF5),
/* GPP_E12: TCHPAD_I2C4_SCL */
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8),
/* GPP_E13: TCHPAD_I2C4_SDA */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8),
/* GPP_E14: NC */
PAD_NC(GPP_E14, NONE),
/* GPP_E15: NC */
PAD_NC(GPP_E15, NONE),
/* GPP_E16: NC */
PAD_NC(GPP_E16, NONE),
/* GPP_E17: GSPI0_CS0 */
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5),
/* GPP_E18: TCHPAD_INT# */
PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, INVERT),
/* GPP_E19: FPMCU_PWREN */
PAD_CFG_GPO(GPP_E19, 1, DEEP),
/* GPP_E20: FPMCU_FW_UPDATE */
PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG),
/* GPP_E21: I2C_PMC_PD_INT_N */
PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
/* GPP_E22: THC0_SPI1_DSYNC */
PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3),
/* GPP_E22: FPS_SOC_INT_L */
PAD_CFG_GPI_IRQ_WAKE(GPP_E22, NONE, PWROK, LEVEL, INVERT),
/* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
@ -246,46 +263,53 @@ static const struct pad_config gpio_table[] = {
/* GPP_F05: CRF_CLKREQ_R */
/* NOTE: IOSSTAGE: 'Ignore' for S0ix */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
/* GPP_F06: WLAN_WWAN_COEX3 */
PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
/* GPP_F07: IMGCLKOUT_2 */
PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
/* GPP_F08: TCH_PNL1_PWR_EN */
PAD_CFG_GPO(GPP_F08, 1, PLTRST),
/* GPP_F06: NC */
PAD_NC(GPP_F06, NONE),
/* GPP_F07: NC */
PAD_NC(GPP_F07, NONE),
/* GPP_F08: EN_TCHSCR_PWR */
PAD_CFG_GPO(GPP_F08, 1, DEEP),
/* GPP_F09: NC */
PAD_NC(GPP_F09, NONE),
/* GPP_F10: PEG_SLOT_PWR_EN_N */
PAD_CFG_GPO(GPP_F10, 0, PLTRST),
/* GPP_F11: MOD_TCSS2_TYP_A_VBUS_EN */
PAD_CFG_GPO(GPP_F11, 1, DEEP),
/* GPP_F12: THC_I2C1_SCL_TCH_PAD */
/* GPP_F10: ISH_GP_6_SNSR_HDR */
PAD_CFG_NF(GPP_F10, NONE, DEEP, NF8),
/* GPP_F11: NC */
PAD_NC(GPP_F11, NONE),
/* GPP_F12: TCHSCR_I2C5_SCL */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
/* GPP_F13: THC_I2C1_SDA_TCH_PAD */
/* GPP_F13: TCHSCR_I2C5_SDA */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
/* GPP_F17: Not used */
PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
/* GPP_F18: TCH_PAD_INT_N */
/* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
/* GPP_F19: GPP_PRIVACY_LED_CAM2 */
PAD_CFG_GPO(GPP_F19, 0, PLTRST),
/* GPP_F20: GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
PAD_CFG_GPO(GPP_F20, 0, PLTRST),
/* GPP_F22: THC1_SPI2_DSYNC */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
/* GPP_F14: GPSI0A_MOSI */
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8),
/* GPP_F15: GSPI0A_MISO */
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8),
/* GPP_F16: TCHSCR_RST_L */
PAD_CFG_GPO(GPP_F16, 1, DEEP),
/* GPP_F17: NC */
PAD_NC(GPP_F17, NONE),
/* GPP_F18: TCHSCR_INT_L */
PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, NONE),
/* GPP_F19: NC */
PAD_NC(GPP_F19, NONE),
/* GPP_F20: NC */
PAD_NC(GPP_F20, NONE),
/* GPP_F22: NC */
PAD_NC(GPP_F22, NONE),
/* GPP_F23: NC */
PAD_NC(GPP_F23, NONE),
/* GPP_H00: Not used */
/* GPP_H00: NC */
PAD_NC(GPP_H00, NONE),
/* GPP_H01: CRD_CAM_STROBE */
PAD_CFG_GPO(GPP_H01, 0, PLTRST),
/* GPP_H02: DEBUG_TRACE_PNP */
PAD_CFG_GPO(GPP_H02, 1, PLTRST),
/* GPP_H03: MIC MUTE */
PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
/* GPP_H04: I2C2_SDA_CAM_FLSH */
PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
/* GPP_H05: I2C2_SCL_CAM_FLSH */
PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
/* GPP_H01: NC */
PAD_NC(GPP_H01, NONE),
/* GPP_H02: NC */
PAD_NC(GPP_H02, NONE),
/* GPP_H03: NC */
PAD_NC(GPP_H03, NONE),
/* GPP_H04: NC */
PAD_NC(GPP_H04, NONE),
/* GPP_H05: NC */
PAD_NC(GPP_H05, NONE),
/* GPP_H06: I2C3_SDA_PSS */
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
/* GPP_H07: I2C3_SCL_PSS */
@ -294,28 +318,28 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09: UART0_BUF_TXD */
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
/* GPP_H10: UART0_BUF_RTS */
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
/* GPP_H11: UART0_BUF_CTS */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
/* GPP_H10: NC */
PAD_NC(GPP_H10, NONE),
/* GPP_H11: NC */
PAD_NC(GPP_H11, NONE),
/* GPP_H13: CPU_C10_GATE_N_R */
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
/* GPP_H14: NC */
PAD_NC(GPP_H14, NONE),
/* GPP_H15: NC */
PAD_NC(GPP_H15, NONE),
/* GPP_H16: WWAN_PWREN */
PAD_CFG_GPO(GPP_H16, 1, PLTRST),
/* GPP_H17: MIC MUTE LED */
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
/* GPP_H19: I3C0_SDA_HDR */
PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
/* GPP_H20: I3C0_SCL_HDR */
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
/* GPP_H21: I2C1_SDA_I3C1_SDA_CAM_FLSH_CVS */
PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
/* GPP_H22: I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */
PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
/* GPP_H16: NC */
PAD_NC(GPP_H16, NONE),
/* GPP_H17: NC */
PAD_NC(GPP_H17, NONE),
/* GPP_H19: NC */
PAD_NC(GPP_H19, NONE),
/* GPP_H20: NC */
PAD_NC(GPP_H20, NONE),
/* GPP_H21: NC */
PAD_NC(GPP_H21, NONE),
/* GPP_H22: NC */
PAD_NC(GPP_H22, NONE),
/* GPP_S00: SNDW3_CLK_CODEC */
PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
@ -325,14 +349,14 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
/* GPP_S03: SNDW3_DATA2_CODEC */
PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
/* GPP_S04: SNDW2_CLK */
PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
/* GPP_S05: SNDW2_DATA0 */
PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
/* GPP_S06: SNDW1_CLK */
PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
/* GPP_S07: SNDW1_DATA0 */
PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
/* GPP_S04: DMIC_CLK_A0 */
PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
/* GPP_S05: DMIC_DATA_0 */
PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
/* GPP_S06: NC */
PAD_NC(GPP_S06, NONE),
/* GPP_S07: NC */
PAD_NC(GPP_S07, NONE),
/* GPP_V00: PM_BATLOW_N */
PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
@ -348,8 +372,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
/* GPP_V06: PM_SLP_A_N */
PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
/* GPP_V07: Not used */
PAD_NC(GPP_V07, NONE),
/* GPP_V07: SUSCLK */
PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1),
/* GPP_V08: SLP_WLAN_N */
PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
/* GPP_V09: PM_SLP_S5_N */
@ -368,8 +392,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
/* GPP_V16: GPP_V16_VCCST_EN */
PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
/* GPP_V17: TCP_RT_S0IX_ENTRY_EXIT_N */
PAD_CFG_GPO(GPP_V17, 1, DEEP),
/* GPP_V17: SLP_S0_GATE_R */
PAD_CFG_GPO(GPP_V17, 1, PLTRST),
};
/* Early pad configuration in bootblock */
@ -378,23 +402,32 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
/* GPP_H09: UART0_BUF_TXD */
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
/* GPP_H06: I2C3_SDA_PSS */
PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
/* GPP_H07: I2C3_SCL_PSS */
PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
/* GPP_D15: SPI_TPM_INT_N */
PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
/* GPP_E02: GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_E02, NONE, PLTRST, LEVEL, INVERT),
};
/* Pad configuration in romstage */
static const struct pad_config romstage_gpio_table[] = {
/* GPP_A08: X1_PCIE_SLOT_PWR_EN */
PAD_CFG_GPO(GPP_A08, 0, PLTRST),
/* GPP_B16: GEN5_SSD_PWREN */
PAD_CFG_GPO(GPP_B16, 1, PLTRST),
/* GPP_C00: GPP_C0_SMBCLK */
PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
/* GPP_C01: GPP_C1_SMBDATA */
PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
/* GPP_E03: GEN5_SSD_RESET_N */
PAD_CFG_GPO(GPP_E03, 1, PLTRST),
/* GPP_E19: FPMCU_PWREN */
PAD_CFG_GPO(GPP_E19, 0, DEEP),
/* GPP_C15: FPS_RST_N */
PAD_CFG_GPO(GPP_C15, 0, DEEP),
/* GPP_F08: EN_TCHSCR_PWR */
PAD_CFG_GPO(GPP_F08, 1, DEEP),
/* GPP_F16: TCHSCR_RST_L */
PAD_CFG_GPO(GPP_F16, 0, DEEP),
};
const struct pad_config *variant_gpio_table(size_t *num)