Previously, the touchscreen IRQ pin was not correctly configured to
GPP_F18_IRQ, which caused an unexpected interrupt storm and led to
the touchscreen becoming unresponsive. This change sets it to the
correct configuration. (schematics version 20250611_v31)
BUG=b:430200649
TEST= Ensure the touchscreen is working properly.
Ensure the interrupt count increases only when the screen is touched
via 'cat /proc/interrupts | grep ELAN'
Change-Id: I20cc9632df76acdfafd2968ece0dde8ee95cc791
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
When battery is not present, reduce power limits to below 45W,avoid
inability to enter the system.
To avoid poor efficiency of the adapter, leave a margin and set the
powerlimit to 38W.
This will check the current battery status and configure cpu power
limits using current PD power value.
BUG=b:418695656
BRANCH=None
TEST=
1、built (emerge-nissa coreboot chromeos-bootimage) and push ap firmware
to dut.
2、Connect 15W machine without battery to 45W adapter and check if it
starts up properly.
3、Use ec command “cbmem -c | grep PL“ to check if the PL4 value is 38
watts.
Log result:[INFO] CPU PL4 = 38 Watts
Change-Id: Iadd43c75ea9235b7ba0e3b97ef460280c13ef1e3
Signed-off-by: Baozhen Yang <yangbaozhen5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Because of internal misunderstanding, modify mipi camera FW_CONFIG
Schematic version: 500E_S3A0_TWL_MB_FVT_20250527
BUG=b:395763555
BRANCH=none
TEST=Boot to OS and verify the mipi camera device are set based on
fw_config.
Change-Id: Id2d62d14bdfd6ad925c5a0c1a9799350a93e57e2
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88352
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Align USB3 Type-A and the related GPIO settings with Pujjolo schematic
(Pujjolo_Pujjoquince_MB_EVT_20250523.pdf).
BUG=b:427962702
TEST= Connect USB 3.0 devices to the Type-A interface and use "lsusb -t"
command to verify the connection
Change-Id: I559dc8105258b91ca89b2f10644e4f95d6a4a085
Signed-off-by: Ben Kao <ben.kao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88290
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit enhances the Kinmen variant of the Fatcat mainboard by
introducing an `fw_config` field for AUDIO. This field includes an
`AUDIO_UNKNOWN` option, providing a clear state when no specific audio
configuration is selected or known.
Furthermore, a probe statement for `AUDIO_ALC721_SNDW` has been added
to the `hda` device. This ensures that the system can correctly identify
and initialize the Realtek ALC721 audio codec when present.
These changes improve the flexibility and accuracy of audio
configuration and detection for the Kinmen board.
BUG=b:430205874
TEST=Able to boot google/kinmen to UI without valid Audio configuration.
Change-Id: I86634a4a49c4006584fc808719b2891186953a51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88367
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces an `AUDIO_UNKNOWN` option to the `fw_config` for
the Francka variant of the Fatcat mainboard. This allows for a default
or fallback state when a specific audio configuration isn't known or
desired.
Additionally, this change introduces audio probe statements that allow
the system to boot successfully even if `FW_CONFIG` is set to
`AUDIO_UNKNOWN`, effectively disabling the audio controller in such
cases.
This prevents boot failures when an unsupported or unknown audio codec
is selected, improving system robustness.
BUG=b:430205874
TEST=Able to boot google/francka to UI without valid Audio
configuration.
Change-Id: I34f7fe5f0509cbddfd3648afb087786373fcf8df
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
This commit modifies the Fatcat mainboard configuration to ensure the
Audio controller is only enabled when a valid `FW_CONFIG` is selected.
This change introduces audio probe statements that allow the
system to boot successfully even if `FW_CONFIG` is set to
`AUDIO_UNKNOWN`, effectively disabling the audio controller in such
cases.
This prevents boot failures when an unsupported or unknown audio codec
is selected, improving system robustness.
BUG=b:430205874
TEST=Able to boot google/fatcat to UI without valid Audio configuration.
Change-Id: I7d1fa07978725129c2651f258894f3590e0a69eb
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88365
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
This patch configures Interrupt, Enable and Reset pins for FPS.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: Ida4fab8da007403898e6843d5161249a5093fd54
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88351
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides option to enable/disable ISH.Removed the
copies and redundant ISH pins from GPIO.c
Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86
BUG=b:394208231
TEST= Build Ocelot and verify it compiles without any error.
Change-Id: I02bfa6b90b1c37a1d69d094804b4153e191a29af
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88329
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes redundant SNDW GPIO mapping that was already present
in fw_config.c and applied as per FW_CONFIG.
BUG=b:427091370
TEST=Boot beep verification is possible using google/fatcat.
Change-Id: Ibeca991b9e855792df48073d2138b9c7ec130c41
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88350
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the CRFP device to use GPIO for the power status. This causes an
ACPI `_STA()` function to be generated that returns the power status of
the CRFP device, rather than always returning `0x1`. This `_STA()`
function can be used during boot to skip enabling the device (and
performing the associated sleep) if the device is already powered on.
BUG=b:428793056
TEST=Boot the board and make sure the FPMCU was booted once
(e.g. examine FPMCU console logs)
TEST=Dump SSDT on kinmen
Scope (\_SB.PCI0.SPI0)
{
Device (CRFP)
{
...
...
PowerResource (PR00, 0x00, 0x0000)
{
Method (_STA, 0, Serialized) // _STA: Status
{
0x5D = \_SB.PCI0.GTXS /* External reference */
Local0
If (!Local0)
{
Return (Zero)
}
0x27 = \_SB.PCI0.GTXS /* External reference */
Local0
Local0 ^= One
If (Local0)
{
Return (Zero)
}
Return (One)
}
Method (_ON, 0, Serialized) // _ON_: Power On
{
Local0 = _STA ()
If ((Local0 == One))
{
Return (Zero)
}
\_SB.PCI0.CTXS (0x27)
\_SB.PCI0.STXS (0x5D)
Sleep (0x03)
\_SB.PCI0.STXS (0x27)
}
Method (_OFF, 0, Serialized) // _OFF: Power Off
{
\_SB.PCI0.CTXS (0x27)
\_SB.PCI0.CTXS (0x5D)
}
}
}
}
Change-Id: Ia3054c61dfab185d124b3aae8df9e80aa6afc71a
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88338
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the necessary configuration for the focaltech
touchscreen (FTSC1000) device, connected to I2C bus 38.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
Datasheet: FT8112_Data_Sheet_V0.2_HKC20240415.pdf
BUG=b:429335394
TEST=emerge-nissa coreboot and focaltech touchscreen can work well.
Change-Id: Ic1c4bea599db23d5bc760bb7a54a2581cb293ce3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88284
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board does not use the board_id-feature hence the code can be
removed.
Change-Id: I18c67580d4611b4c53248315937277bed53bd1ea
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This mainboard does not have an embedded controller (EC), therefore
remove the code for it.
Change-Id: Ib37b3cc257f7ac4af6a6505a3e43c9e5275fcd3f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88262
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard will just have a single VBT in cbfs which will be named
as the default name is (vbt.bin). There is no need to chose between
different configurations for the VBT selection. Therefore, remove the
corresponding code.
Change-Id: Ia72e8bae23c15476c362e456dc8358bec3b102a5
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This mainboard is not going to use Type-C subsystem. Therefore, disable
and remove the config data for it.
Change-Id: I2d9e53bf63b41811040f84cfe9dedf275f1059e4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88260
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Siemens boards store their memory configuration data (SPD) in a field
inside the HWInfo block (which itself is located in CBFS). This patch
removes all *spd.hex-files and uses HWInfo instead for the SPD data
source. In addition, the memory data swizzling is updated to reflect
the board wiring so that DRAM can work properly.
Change-Id: I63d6e7c4543b7d99a4b1815c8ee81efcb6a87b94
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
While reviewing CB:87192 that deals with this option on another
mainboard, it was found that northbridge/intel/sandybridge
actually could not handle this option (present on Ivy Bridge
only anyway) properly. It would only factor 544MB into memory
calculations while telling IGD it can use 1024MB.
Until a fix can be implemented there, remove this option from
Ivy Bridge mainboards.
Change-Id: I0c87c52ef050cca54e050de3d41603c4ab29740b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88294
Reviewed-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Values here above 512M are:
1. Inconsistent with Intel IVB datasheet vol.2, document #326765;
2. Apparently not properly supported by nb/intel/sandybridge.
Take them out until a fix can be implemented.
Change-Id: I6183f447af2816d00c9f6d78329113cd9c584191
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88293
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board is missing option values for 256MB and up.
Make complete by referencing asus/p8x7x-series and Intel IVB
datasheet vol.2, document #326765.
Intel datasheet lists an additional 1GB option for Ivy Bridge
CPUs, but since nb/intel/sandybridge/northbridge.c has been
found to not handle this setting properly when doing memory
calculations, a fix is needed there before it can be included.
It was not an option for Sandy Bridge anyway.
BUG=https://ticket.coreboot.org/issues/581
Change-Id: Id89290a673b0e5dbc72c11c097aeb70d410adeab
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Recent development of the "pro_6300" variant fixed the 4th sata port,
using "register sata_port_map" = "0x17" in "overridetree.cb" the same
is valid for the following 2 variants:
- compaq_8300_elite_sff
- compaq_8200_elite_sff
BUG=581#note-22
TEST=grub2 output & dmesg output
p4
�����������������������������������������
� Boot Menu �
�����������������������������������������
Device Path :
Select a Boot Device PciRoot(0x0)/Pci(0x1F,
0x2)/Sata(0x4,0xFFFF,0
UEFI Shell x0)
USB Device
SATA: hp DVD A DH16ABSH
dmesg | grep SATA | grep link
[ 4.994271] ata1: SATA link down (SStatus 0 SControl 300)
[ 5.304068] ata2: SATA link down (SStatus 0 SControl 300)
[ 5.616102] ata3: SATA link down (SStatus 0 SControl 300)
[ 5.920122] ata5: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
Change-Id: Idcef5854e1e97380bec12374411ddfdb50395c29
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88304
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When battery is not present, reduce power limits to below 45W,
avoid inability to enter the system.
To avoid poor efficiency of the adapter, leave a margin and set the powerlimit to 38w.
This will check the current battery status and configure cpu power
limits using current PD power value.
BUG=b:418695656
BRANCH=None
TEST=
1、built(emerge-nissa coreboot chromeos-bootimage) and push ap firmware to dut.
2、Connect 15W machine without battery to 45W adapter and check if it starts up properly.
3、Use ec command “cbmem -c | grep PL“ to check if the PL4 value is 38 watts.
Change-Id: I72429052f5b3d25e56076176728498357a298cdd
Signed-off-by: Baozhen Yang <yangbaozhen5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88282
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The IOT version of FSP is inconsistent at resuming from S3,
so switch to the client version.
Change-Id: Ifadfebf53e20bc82e6272ea28e5bc443b9829545
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88055
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Enable Realtek ALC722 and ALC1320 soundwire codec for francka.
Refer to the main board schematic(1224A) and
audio board schematic(1106A).
BUG=b:420516709
TEST=Build and boot and check the ssdt dump PCI0.HDAS.SNDW.
Scope (\_SB.PCI0.HDAS.SNDW)
Device (SW00)
Name (_ADR, 0x000030025D072201) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Scope (\_SB.PCI0.HDAS.SNDW)
Device (SW20)
Name (_ADR, 0x000230025D132001) // _ADR: Address
Name (_DDN, "Speaker Amp") // _DDN: DOS Device Name
Scope (\_SB.PCI0.HDAS.SNDW)
Device (SW30)
Name (_ADR, 0x000330025D132001) // _ADR: Address
Name (_DDN, "Speaker Amp") // _DDN: DOS Device Name
Change-Id: I542d94fd792272d3b7d75538671ba2f59c331a1e
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88022
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Because of the internal misunderstanding, so now correct the right fw
config of wifi SAR id number from 18 to 21 to 17 to 20.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS and check coreboot log to check the wifi SAR table could work fine.
Change-Id: Ib006996fb8887a36feb5dfe71baef58fa74c35f7
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88200
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The power LED may be disabled by GPP_D1. The pin is PWM capable, so
configure it in PWM mode with a frequency of 0.5Hz, duty cycle of 50%
when entering sleep.
The result is that the power LED toggles on/off every second.
TEST=Boot to Windows 10, enter S3, and wake. The power LED will blink
when system is asleep and glow continuously when awake.
Change-Id: I121e0ef3e47aec1cacdace3f2af47a3fdacf69cf
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Correct UART1 TX/RX pad configuration in early_gpio.c from NF2
to NF1. This enables proper UART1 signaling on GPP_D17 and GPP_D18
when operating in native mode.
This change is based on guidance from Intel Doc. No. 648094.
TEST=Patched and booted board. Confirmed UART1 communication
works via serial adapter. Loopback test passed.
Change-Id: Ib1f5ee17e6f3d8a845d024e6b8593606b0430b6f
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88195
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updated DDI port configuration to properly enable eDP (Port A)
and HDMI (Port B) with HPD and DDC settings on LattePanda MU.
This change ensures both internal and external displays are
detected and initialized correctly during boot.
Change-Id: I84e5bc4b8a26f58b9cb26a4018eef640ac245e7f
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88194
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Intel PMC and ACPI IPC interface in Kconfig to fix
power-off failure on shutdown.
Previously, the system failed to fully power off after shutdown,
leaving some power rails active and preventing restart via the
power button. A full power cycle was required to reboot.
This change ensures proper system power-off behavior.
TEST=Tested shutdown behavior with PMC and ACPI IPC interface
enabled in Kconfig. System now powers off cleanly and can restart
via power button without unplugging power
Verify OS: Ubuntu 24.04
Change-Id: I1f93410bcd717630319adabec40534b5b7467582
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88193
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add `board.fmd` and update Kconfig to define FMDFILE for
LattePanda MU.
This file describes the flash layout including
- Flash Descriptor
- ME
- MRC_CACHE
- SMMSTORE
- CBFS
TEST=Built mb/lattepanda/mu with and without board.fmd.
Adjusting FMAP layout via board.fmd changes section sizes and offsets.
This affects the position and size of the COREBOOT (CBFS) region in
the final ROM image.
With board.fmd:
- FMAP layout explicitly defines COREBOOT size and offset
- build log shows detailed FMAP section breakdown, including
CBFS region
Sample log excerpt:
'COREBOOT' (CBFS, size 3865600, offset 12911616)
Without board.fmd:
- default FMAP layout is applied
- COREBOOT region is located differently
with board.fmd
```
Writing new image to build/coreboot.pre
UPDATE-FIT set FIT pointer to table
UPDATE-FIT Microcode
CBFS coreboot.rom
FIT table:
Index Type Addr Size
0 Microcode 0xffc504b0 0x00000000
CBFSLAYOUT coreboot.rom
This image contains the following sections that can be manipulated
with this tool:
'SI_DESC' (size 4096, offset 0)
'SI_ME' (size 4272128, offset 4096)
'SI_PDR' (size 2015232, offset 4276224)
'RW_MRC_CACHE' (size 65536, offset 12582912)
'SMMSTORE' (size 262144, offset 12648448)
'COREBOOT' (CBFS, size 3865600, offset 12911616)
...
Built lattepanda/mu (MU_8G)
```
without 'board.fmd'
```
Writing new image to build/coreboot.pre
UPDATE-FIT set FIT pointer to table
UPDATE-FIT Microcode
CBFS coreboot.rom
FIT table:
Index Type Addr Size
0 Microcode 0xffc502b0 0x00000000
CBFSLAYOUT coreboot.rom
This image contains the following sections that can be manipulated
with this tool:
'SI_DESC' (size 4096, offset 0)
'SI_ME' (size 4272128, offset 4096)
'SI_DEVICEEXT2' (size 2015232, offset 4276224)
'RW_MRC_CACHE' (size 65536, offset 12582912)
'SMMSTORE' (size 262144, offset 12648448)
'COREBOOT' (CBFS, size 3866112, offset 12911104)
...
Built lattepanda/mu (MU_8G)
```
Change-Id: If197679c8359f5f75ab125b0c8600926611ac57b
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88192
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add eDP panel power-on sequences and initialize the display in the
ramstage. Also Set display registers to normal mode if initialization
flow is skipped to prevent abnormal behavior.
BUG=b:400886838,b:422507985
BRANCH=none
TEST=utility gbb --set --flash --flags=0x39, and check the firmware
screen.
utility gbb --set --flash --flags=0x0, and check the DUT screen.
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.corp-partner.google.com>
Change-Id: I09edceefee9c17ce18681b85da8ca75f65ed2876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88273
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the EC host command range configuration for Ocelot
board variants, ensuring that each variant uses the correct range based
on its specific EC.
BOARD_GOOGLE_OCELOTMCHP and BOARD_GOOGLE_OCELOTMCHP4ES uses Microchip
EC.
BOARD_GOOGLE_OCELOT and BOARD_GOOGLE_OCELOT4ES uses Nuvoton EC.
BOARD_GOOGLE_OCELOTITE and BOARD_GOOGLE_OCELOTITE4ES uses ITE EC.
Key changes:
- Microchip EC: Configured to use host command ranges 0x800-0x807 and
0x200-0x20f. The register is set to 0x00040801 to accommodate these
constraints.
BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.
Change-Id: If08f2362a7b3bafca69375ce3b346f75435a83df
Signed-off-by: P, Usha <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88179
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A compaq_8300_elite_sff build can run on these models mostly unmodified.
Spawn a new variant from it, tie up some obvious loose ends and bring it
officially into the fold.
BUG=https://ticket.coreboot.org/issues/581
Change-Id: Ic0f04d586a8361968d7f6c3e3d048f945528cb84
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add support for the Memsic MXC6655 accelerometer on I2C0, as an
alternative to the existing Kionix KCXJ9. Use the "detect" function
of the I2C generic driver to determine which is present at runtime.
TEST=build/boot starlite_adl with MXC6655, verify screen roation works
properly when detached from keyboard under Linux and Windows.
Change-Id: I59d424903cceda9871855372e1d666eaa12443b0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This commit refines the ROM size configuration for Google Bluey
mainboards by moving the `BOARD_ROMSIZE_KB_*` selection from the
common Kconfig to the specific board variants.
Previously, `BOARD_ROMSIZE_KB_65536` was selected for
`BOARD_GOOGLE_BLUEY_COMMON`. This blanket setting is inaccurate as
different Bluey-based boards utilize different sized ROMs.
With this change:
- `BOARD_GOOGLE_BLUEY` now selects `BOARD_ROMSIZE_KB_65536`.
- `BOARD_GOOGLE_QUENBI` now selects `BOARD_ROMSIZE_KB_32768`.
This ensures that each board variant has the correct ROM size
configured, preventing potential issues related to image size or
flash programming.
TEST=Able to verify that google/bluey AP FW image os 64MB and
google/quenbi AP FW is 32MB in size.
Change-Id: Ifcf75b310f08cbc4bbbd27ad7947df06da4f5d5a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors the SPI flash vendor selection for Google Bluey
boards to accurately reflect the components used by each variant.
Previously, `SPI_FLASH_WINBOND` was unconditionally selected for
`BOARD_GOOGLE_BLUEY_COMMON`. This is incorrect as different Bluey
variants may use different SPI flash chips.
This change now specifically selects:
- `SPI_FLASH_MACRONIX` for `BOARD_GOOGLE_BLUEY`
- `SPI_FLASH_WINBOND` for `BOARD_GOOGLE_QUENBI`
This ensures that the correct SPI flash driver is enabled for each
specific board variant, as per underlying hardware design.
TEST=Able to build google/bluey.
Change-Id: I7deaed90a7f6533ed4fe9fd815715dabdaa561a3
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
enable_power_saving is a boolean so use "true" "false".
Change-Id: I0f62fc2b0db3abd3f204951f15081b89e02a0754
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86608
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
brox_rtk_ec share the same power design with brox,
so follow brox set as 9W.
BUG=b:414474440
TEST=system can boot when AC only.
Change-Id: Ia05b331f229127b898f4549d5ba1ac2771ac8b7b
Signed-off-by: Elmo Lan <elmo_lan@realtek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Follow baseboard nissa and project pujjocento project to setting
GPE configuration.
BUG=b:395763555
BRANCH=none
TEST=Build and boot to OS.
Change-Id: I75deadd0c1b7218c2d0820d637cc2ec02bf9154f
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88199
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace `data.vbt` with version from Intel FSP repository to match
the updated FSP release used in this platform.
This change is required when using 3rdparty/fsp/AlderLakeFspBinPkg
commit: 15848ee4934acbd94069454f369e9869bb0f1295
which introduces the "IoT ADL-N IPU25.3 (6114_00)" release.
With the previous VBT, the system boots but fails to display
any graphics output (HDMI) during firmware POST and OS boot.
This updated VBT resolves the display initialization issue.
Source:
15848ee493/AlderLakeFspBinPkg/IoT/AlderLakeN/Vbt/Vbt_ADLN.bin
Change-Id: If948d3bbef02f516067db0bad07167bdf7c81ce2
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88191
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Fn key on kinmen emits a scancode of 94 (0x5e).
BUG=b:409148565
TEST=Flash kinmen, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`
Change-Id: If919c6f421719e06399620b17e1f4f5a161a7de2
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88207
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
