mb/siemens/mc_rpl: Remove unused embedded controller code
This mainboard does not have an embedded controller (EC), therefore remove the code for it. Change-Id: Ib37b3cc257f7ac4af6a6505a3e43c9e5275fcd3f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88262 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Kilian Krause <kilian.krause@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Werner Zeh
Matt DeVillier
parent
a1067ec6de
commit
5de16ed1b8
6 changed files with 0 additions and 176 deletions
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@ -1,14 +1,5 @@
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chip soc/intel/alderlake
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# This disables autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses.
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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@ -1,7 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#include <baseboard/ec.h>
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#include <baseboard/gpio.h>
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DefinitionBlock(
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@ -23,16 +22,5 @@ DefinitionBlock(
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#include <soc/intel/alderlake/acpi/southbridge.asl>
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}
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#if CONFIG(EC_GOOGLE_CHROMEEC)
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/* ChromeOS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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}
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#endif
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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}
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@ -1,72 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __BASEBOARD_EC_H__
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#define __BASEBOARD_EC_H__
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#include <ec/ec.h>
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#include <ec/google/chromeec/ec_commands.h>
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#include <baseboard/gpio.h>
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#define MAINBOARD_EC_SCI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
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#define MAINBOARD_EC_SMI_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
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/* EC can wake from S5 with lid or power button */
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#define MAINBOARD_EC_S5_WAKE_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
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/*
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* EC can wake from S3 with lid or power button or key press or AC connect/disconnect or
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* mode change event.
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*/
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#define MAINBOARD_EC_S3_WAKE_EVENTS \
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(MAINBOARD_EC_S5_WAKE_EVENTS |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
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#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
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/* Log EC wake events plus EC shutdown events */
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#define MAINBOARD_EC_LOG_EVENTS \
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(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
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EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
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/*
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* ACPI related definitions for ASL code.
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*/
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/* Enable EC backed ALS device in ACPI */
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#define EC_ENABLE_ALS_DEVICE
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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/* Enable LID switch and provide wake pin for EC */
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#define EC_ENABLE_LID_SWITCH
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#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
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#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
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#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
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#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
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#endif /* __BASEBOARD_EC_H__ */
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@ -6,12 +6,4 @@
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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/* eSPI virtual wire reporting */
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#define EC_SCI_GPI GPE0_ESPI
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/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
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#define GPE_EC_WAKE GPE0_LAN_WAK
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#define GPIO_EC_IN_RW GPP_E7
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#endif /* __BASEBOARD_GPIO_H__ */
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@ -2,34 +2,15 @@
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <cpu/cpu.h>
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#include <cpu/intel/cpu_ids.h>
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#include <device/device.h>
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#include <ec/ec.h>
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#include <fw_config.h>
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#include <smbios.h>
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#include <soc/gpio.h>
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#include <stdint.h>
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#include <stdio.h>
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#include "board_id.h"
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const char *smbios_system_sku(void)
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{
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static char sku_str[7] = "";
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uint8_t sku_id = get_board_id();
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snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id);
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return sku_str;
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}
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static void mainboard_init(void *chip_info)
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{
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variant_configure_gpio_pads();
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if (CONFIG(EC_GOOGLE_CHROMEEC))
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mainboard_ec_init();
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variant_devtree_update();
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}
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@ -38,32 +19,6 @@ void __weak variant_devtree_update(void)
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/* Override dev tree settings per board */
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}
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#if CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
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static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
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{
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struct smbios_type11 *t;
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char buffer[64];
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t = (struct smbios_type11 *)arg;
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snprintf(buffer, sizeof(buffer), "%s-%s", config->field_name, config->option_name);
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t->count = smbios_add_string(t->eos, buffer);
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}
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static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t)
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{
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fw_config_for_each_found(add_fw_config_oem_string, t);
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}
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#endif
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static void mainboard_enable(struct device *dev)
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{
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#if CONFIG(BOARD_INTEL_ADLRVP_N_EXT_EC)
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dev->ops->get_smbios_strings = mainboard_smbios_strings;
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#endif
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = mainboard_enable,
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};
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@ -1,30 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <cpu/x86/smm.h>
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#include <ec/google/chromeec/smm.h>
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#include <intelblocks/smihandler.h>
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#include <baseboard/ec.h>
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void mainboard_smi_espi_handler(void)
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{
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if (!CONFIG(EC_GOOGLE_CHROMEEC))
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return;
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chromeec_smi_process_events();
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}
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void mainboard_smi_sleep(u8 slp_typ)
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{
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if (!CONFIG(EC_GOOGLE_CHROMEEC))
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return;
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chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
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}
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int mainboard_smi_apmc(u8 apmc)
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{
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if (CONFIG(EC_GOOGLE_CHROMEEC))
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chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
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return 0;
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}
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