mb/lenovo/m900_tiny: enable power LED blink in S3 and S4

The power LED may be disabled by GPP_D1. The pin is PWM capable, so
configure it in PWM mode with a frequency of 0.5Hz, duty cycle of 50%
when entering sleep.

The result is that the power LED toggles on/off every second.

TEST=Boot to Windows 10, enter S3, and wake. The power LED will blink
when system is asleep and glow continuously when awake.

Change-Id: I121e0ef3e47aec1cacdace3f2af47a3fdacf69cf
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Michał Kopeć 2024-10-24 19:42:45 +02:00 committed by Matt DeVillier
commit dabc200abb
4 changed files with 33 additions and 1 deletions

View file

@ -12,3 +12,5 @@ ramstage-y += gpio.c
ramstage-y += hda_verb.c
ramstage-y += ramstage.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
smm-y += smihandler.c

View file

@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPP_D ------- */
PAD_NC(GPP_D0, NONE),
PAD_NC(GPP_D1, NONE),
PAD_CFG_NF(GPP_D1, NONE, DEEP, NF4), /* PW_LED# (blink mode)*/
PAD_NC(GPP_D2, NONE),
PAD_NC(GPP_D3, NONE),
PAD_NC(GPP_D4, NONE),

View file

@ -5,8 +5,10 @@
#include <device/pci_def.h>
#include <drivers/intel/gma/int15.h>
#include <gpio.h>
#include <intelblocks/pcr.h>
#include <mainboard/gpio.h>
#include <option.h>
#include <soc/pcr_ids.h>
#include <soc/ramstage.h>
#include <static.h>
#include <superio/nuvoton/nct6687d/nct6687d.h>
@ -73,6 +75,12 @@ static void mainboard_enable(struct device *dev)
mainboard_configure_gpios();
devtree_update();
print_board_id();
/* Configure GPIO community 1 PWM frequency to 0.5Hz, 0% duty cycle */
pcr_write32(PID_GPIOCOM1, 0x204, (1 << 14));
/* Set the software update flag */
pcr_or32(PID_GPIOCOM1, 0x204, (1 << 30));
/* Enable PWM */
pcr_or32(PID_GPIOCOM1, 0x204, (1 << 31));
}
struct chip_operations mainboard_ops = {

View file

@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
#include <cpu/x86/smm.h>
#include <intelblocks/pcr.h>
#include <soc/pcr_ids.h>
void mainboard_smi_sleep(u8 slp_typ)
{
/* Enable blinking power LED when entering S3 or S4 */
switch (slp_typ) {
case ACPI_S3:
case ACPI_S4:
/* Configure GPIO community 1 PWM duty cycle to 50% */
pcr_rmw32(PID_GPIOCOM1, 0x204, 0xffffff00, 0x7f);
/* Set the software update flag */
pcr_or32(PID_GPIOCOM1, 0x204, (1 << 30));
break;
default:
break;
}
}