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mb/google/ocelot/var/ocelot: Configure FPS related changes

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This patch configures Interrupt, Enable and Reset pins for FPS.

BUG=b:394208231
TEST=Build Ocelot and verify it compiles without any error.

Change-Id: Ida4fab8da007403898e6843d5161249a5093fd54
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88351
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sowmya Aralguppe 2025-07-08 10:47:41 +05:30 • committed by Matt DeVillier
commit 0ef670a66a
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/google/ocelot/variants/ocelot/overridetree.cb
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@ -558,11 +558,11 @@ chip soc/intel/pantherlake
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)"
register "wake" = "GPE0_DW1_01"
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E19_IRQ)"
register "wake" = "GPE0_DW1_19"
register "has_power_resource" = "true"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E05)"
register "enable_delay_ms" = "3"
device spi 0 on
probe FP FP_PRESENT