mb/google/ocelot/var/ocelot: Add FW_CONFIG for Audio
Add FW_CONFIG probe based on Ocelot for Audio device: 1.HDA Interface 2.SNDW Interface 3.DMIC - 2 Schematic version: schematic_1433518 Platform Mapping Document : Rev0p86 BUG=b:394208231 TEST= Build Ocelot and verify it compiles without any error. Change-Id: Ideea34defdb6f4da63374ae09e2088c3de745657 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Avi Uday <aviuday@google.com>
This commit is contained in:
Sowmya Aralguppe
Matt DeVillier
parent
f323adb19f
commit
95784dbafb
1 changed files with 48 additions and 69 deletions
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@ -12,92 +12,77 @@
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#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t))
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static const struct pad_config hda_enable_pads[] = {
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/* HDA_BCLK */
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/* GPP_D10: HDA_BCLK (HDR) */
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PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
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/* HDA_SYNC */
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PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1),
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/* HDA_SDO */
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PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1),
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/* HDA_SDI_0 */
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PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1),
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/* DMIC_CLK */
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/* GPP_D11: HDA_SYNC (HDR) */
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PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
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/* GPP_D12: HDA_SDO (HDR) */
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PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
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/* GPP_D13: HDA_SDI0 (HDR) */
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PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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/* GPP_D16: HDA_RST_N (HDR) */
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PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
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/* GPP_D17: HDA_SDI1 (HDR) */
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PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
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/* GPP_S04: DMIC0_CLK (HDR) */
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PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
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/* DMIC_DATA */
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/* GPP_S05: DMIC0_DATA (HDR) */
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PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
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};
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static const struct pad_config bt_i2s_enable_pads[] = {
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/* GPP_V30 : [] ==> BT_I2S_BCLK - SSP2 */
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PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3),
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/* GPP_V31 : [] ==> BT_I2S_SYNC - SSP2 */
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PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3),
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/* GPP_V32 : [] ==> BT_I2S_SDO - SSP2 */
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PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3),
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/* GPP_V33 : [] ==> BT_I2S_SDI - SSP2 */
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PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3),
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/* GPP_V34 : [] ==> SSP_SCLK */
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PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1),
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/* GPP_V35 : [] ==> SSP_SFRM */
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PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1),
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/* GPP_V36 : [] ==> SSP_TXD */
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PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1),
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/* GPP_V37 : [] ==> SSP_RXD */
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PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1),
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};
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static const struct pad_config bt_i2s_disable_pads[] = {
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/* GPP_V30 : [] ==> BT_I2S_BCLK */
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PAD_NC(GPP_VGPIO30, NONE),
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/* GPP_V31 : [] ==> BT_I2S_SYNC */
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PAD_NC(GPP_VGPIO31, NONE),
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/* GPP_V32 : [] ==> BT_I2S_SDO */
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PAD_NC(GPP_VGPIO32, NONE),
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/* GPP_V33 : [] ==> BT_I2S_SDI */
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PAD_NC(GPP_VGPIO33, NONE),
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/* GPP_V34 : [] ==> SSP2_SCLK */
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PAD_NC(GPP_VGPIO34, NONE),
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/* GPP_V35 : [] ==> SSP2_SFRM */
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PAD_NC(GPP_VGPIO35, NONE),
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/* GPP_V36 : [] ==> SSP_TXD */
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PAD_NC(GPP_VGPIO36, NONE),
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/* GPP_V37 : [] ==> SSP_RXD */
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PAD_NC(GPP_VGPIO37, NONE),
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/* GPP_S06: DMIC1_CLK (HDR) */
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PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
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/* GPP_S07: DMIC1_DATA (HDR) */
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PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
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};
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static const struct pad_config sndw_alc721_enable_pads[] = {
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/* SNDW3_CLK */
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/* Soundwire GPIO Config */
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/* GPP_S00: SNDW3_CLK_CODEC (HDR) */
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PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
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/* SNDW3_DATA0 */
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/* GPP_S01: SNDW3_DATA0_CODEC (HDR) */
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PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
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/* SNDW3_DATA1 */
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/* GPP_S02: SNDW3_DATA1_CODEC (HDR) */
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PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
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/* SNDW3_DATA2 */
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/* GPP_S03: SNDW3_DATA2_CODEC (HDR) */
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PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
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/* DMIC_CLK_A0 */
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/* GPP_S04: DMIC0_CLK (HDR) */
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PAD_CFG_NF(GPP_S04, NONE, DEEP, NF5),
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/* DMIC_DATA_0 */
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/* GPP_S05: DMIC0_DATA (HDR) */
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PAD_CFG_NF(GPP_S05, NONE, DEEP, NF5),
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/* SNDW1_CLK */
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PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
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/* SNDW1_DATA */
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PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
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/* GPP_S06: DMIC1_CLK (HDR) */
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PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5),
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/* GPP_S07: DMIC1_DATA (HDR) */
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PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5),
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};
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static const struct pad_config audio_disable_pads[] = {
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PAD_NC(GPP_S00, NONE),
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PAD_NC(GPP_S01, NONE),
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PAD_NC(GPP_S02, NONE),
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PAD_NC(GPP_S03, NONE),
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PAD_NC(GPP_S04, NONE),
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PAD_NC(GPP_S05, NONE),
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PAD_NC(GPP_S06, NONE),
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PAD_NC(GPP_S07, NONE),
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PAD_NC(GPP_D09, NONE),
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/* GPP_D10: HDA_BCLK (HDR) */
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PAD_NC(GPP_D10, NONE),
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/* GPP_D11: HDA_SYNC (HDR) */
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PAD_NC(GPP_D11, NONE),
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/* GPP_D12: HDA_SDO (HDR) */
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PAD_NC(GPP_D12, NONE),
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/* GPP_D13: HDA_SDI0 (HDR) */
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PAD_NC(GPP_D13, NONE),
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/* GPP_D16: HDA_RST_N (HDR) */
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PAD_NC(GPP_D16, NONE),
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/* GPP_D17: HDA_SDI1 (HDR) */
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PAD_NC(GPP_D17, NONE),
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/* GPP_S00: SNDW3_CLK_CODEC (HDR) */
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PAD_NC(GPP_S00, NONE),
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/* GPP_S01: SNDW3_DATA0_CODEC (HDR) */
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PAD_NC(GPP_S01, NONE),
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/* GPP_S02: SNDW3_DATA1_CODEC (HDR) */
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PAD_NC(GPP_S02, NONE),
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/* GPP_S03: SNDW3_DATA2_CODEC (HDR) */
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PAD_NC(GPP_S03, NONE),
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/* GPP_S04: DMIC0_CLK (HDR) */
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PAD_NC(GPP_S04, NONE),
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/* GPP_S05: DMIC0_DATA (HDR) */
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PAD_NC(GPP_S05, NONE),
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/* GPP_S06: DMIC1_CLK (HDR) */
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PAD_NC(GPP_S06, NONE),
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/* GPP_S07: DMIC1_DATA (HDR) */
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PAD_NC(GPP_S07, NONE),
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};
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static const struct pad_config x1slot_pads[] = {
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@ -473,16 +458,10 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
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if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_NONE))) {
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GPIO_PADBASED_OVERRIDE(padbased_table, audio_disable_pads);
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GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
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} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) {
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printk(BIOS_INFO, "Configure GPIOs for Soundwire audio.\n");
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GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc721_enable_pads);
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printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n");
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GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads);
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} else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
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printk(BIOS_INFO, "Configure GPIOs for HDA ALC 256 mode.\n");
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GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads);
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GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads);
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}
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if (fw_config_probe(FW_CONFIG(WIFI, WIFI_PCIE_6)) ||
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