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mb/trulo/var/pujjolo: Correct USB3 Type-A OC pins

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Align USB3 Type-A and the related GPIO settings with Pujjolo schematic
(Pujjolo_Pujjoquince_MB_EVT_20250523.pdf).

BUG=b:427962702
TEST= Connect USB 3.0 devices to the Type-A interface and use "lsusb -t"
 command to verify the connection

Change-Id: I559dc8105258b91ca89b2f10644e4f95d6a4a085
Signed-off-by: Ben Kao <ben.kao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88290
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Ben Kao 2025-07-03 19:26:20 +08:00 • committed by Matt DeVillier
commit 4f5f75da34
2 changed files with 6 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

8
src/mainboard/google/brya/variants/pujjolo/gpio.c
View file

@ -30,10 +30,10 @@ static const struct pad_config override_gpio_table[] = {
PAD_CFG_GPI_SCI_HIGH(GPP_A12, NONE, PLTRST, EDGE_BOTH),
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
/* A14 : USB_OC1# */
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* A15 : USB_OC2# */
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
/* A14 : USB_OC1# ==> NC */
PAD_NC(GPP_A14, NONE),
/* A15 : USB_OC2# ==> NC */
PAD_NC(GPP_A15, NONE),
/* A16 : USB_OC3# ==> NC */
PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
/* A17 : NC */

4
src/mainboard/google/brya/variants/pujjolo/overridetree.cb
View file

@ -66,8 +66,8 @@ chip soc/intel/alderlake
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3 Type-A port A0(MLB))
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3 Type-A port A1(DB)
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A0(MLB))
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 Type-A port A1(DB)
#register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN