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mb/google/ocelot/var/ocelot: Add FW_CONIG for ISH

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This patch provides option to enable/disable ISH.Removed the
copies and redundant ISH pins from GPIO.c

Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86

BUG=b:394208231
TEST= Build Ocelot and verify it compiles without any error.

Change-Id: I02bfa6b90b1c37a1d69d094804b4153e191a29af
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88329
Reviewed-by: Avi Uday <aviuday@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sowmya Aralguppe 2025-07-06 18:08:26 +05:30 • committed by Matt DeVillier
commit 410b3c697f
2 changed files with 44 additions and 35 deletions
Download patch file Download diff file Expand all files Collapse all files

47
src/mainboard/google/ocelot/variants/ocelot/fw_config.c
View file

@ -346,20 +346,44 @@ static const struct pad_config thc1_enable_wake[] = {
};
static const struct pad_config ish_disable_pads[] = {
/* GPP_D06: NC */
/* GPP_B05: C_EC_ISH_ALRT */
PAD_NC(GPP_B05, NONE),
/* GPP_B07: SLATEMODE_HALLOUT_SNSR_R */
PAD_NC(GPP_B07, NONE),
/* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */
PAD_NC(GPP_B18, NONE),
/* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */
PAD_NC(GPP_B19, NONE),
/* GPP_B22: ISH_GP_5_SNSR_HDR */
PAD_NC(GPP_B22, NONE),
/* GPP_B23: ISH_GP_6_SNSR_HDR */
PAD_NC(GPP_B23, NONE),
/* GPP_D05: ISH_UART0_ECAIC_RXD */
PAD_NC(GPP_D05, NONE),
/* GPP_D06: ISH_UART0_ECAIC_TXD */
PAD_NC(GPP_D06, NONE),
/* GPP_E05: NC */
PAD_NC(GPP_E05, NONE),
/* GPP_F23: NC */
/* GPP_F23: SMC_LID / ISH_GP9A*/
PAD_NC(GPP_F23, NONE),
};
static const struct pad_config ish_enable_pads[] = {
/* GPP_D06: ISH_UART0_TXD */
/* GPP_B05: C_EC_ISH_ALRT */
PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
/* GPP_B07: SLATEMODE_HALLOUT_SNSR_R */
PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
/* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
/* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
/* GPP_B22: ISH_GP_5_SNSR_HDR */
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
/* GPP_B23: ISH_GP_6_SNSR_HDR */
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
/* GPP_D05: ISH_UART0_ECAIC_RXD */
PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
/* GPP_D06: ISH_UART0_ECAIC_TXD */
PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
/* GPP_E05: ISH_GP_7_SNSR_HDR */
PAD_CFG_NF(GPP_E05, NONE, DEEP, NF4),
/* GPP_F23: ISH_GP_9A */
/* GPP_F23: SMC_LID / ISH_GP9A*/
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF8),
};
@ -506,10 +530,11 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads);
}
if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE)))
GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
else
if (fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) {
GPIO_PADBASED_OVERRIDE(padbased_table, ish_enable_pads);
} else {
GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads);
}
/* NOTE: disable PEG (x8 slot) and x4 slot wake for now */
GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads);

32
src/mainboard/google/ocelot/variants/ocelot/gpio.c
View file

@ -50,17 +50,15 @@ static const struct pad_config gpio_table[] = {
/* GPP_B01: USBC_SML_DATA_PD */
PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
/* GPP_B02: ISH_I2C0_SDA_SNSR_HDR */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
PAD_NC(GPP_B02, NONE),
/* GPP_B03: ISH_I2C0_SCL_SNSR_HDR */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
PAD_NC(GPP_B03, NONE),
/* GPP_B04: ISH_GP_0_SNSR_HDR */
PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
PAD_NC(GPP_B04, NONE),
/* GPP_B06: SOC_PDB_CTRL */
PAD_CFG_GPO(GPP_B06, 0, DEEP),
/* GPP_B07: SLATEMODE_HALLOUT_SNSR_R */
PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
/* GPP_B08: ISH_GP_4_SNSR_HDR */
PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
PAD_NC(GPP_B08, NONE),
/* GPP_B09: BT_RF_KILL_N */
PAD_CFG_GPO(GPP_B09, 1, DEEP),
/* GPP_B10: NC */
@ -75,18 +73,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_B16, NONE, DEEP),
/* GPP_B17: SPI_TPM_INT_N */
PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
/* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
/* GPP_B20: WWAN_RST_N */
PAD_CFG_GPO(GPP_B20, 1, PLTRST),
/* GPP_B21: TCP_RETIMER_FORCE_PWR */
PAD_CFG_GPO(GPP_B21, 0, DEEP),
/* GPP_B22: ISH_GP_5_SNSR_HDR */
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
/* GPP_B23: ISH_GP_6_SNSR_HDR */
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
/* GPP_B24: ESPI_ALERT0_EC_R_N */
PAD_NC(GPP_B24, NONE),
/* GPP_B25: None */
@ -145,14 +135,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_D02, 0, DEEP),
/* GPP_D03: X4_SLOT_WAKE_N */
PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL),
/* GPP_D05: ISH_UART0_ECAIC_RXD */
PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
/* GPP_D06: ISH_UART0_ECAIC_TXD */
PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2),
/* GPP_D07: ISH_UART0_RTS_N_SNSR_HDR */
PAD_CFG_NF(GPP_D07, NONE, DEEP, NF3),
PAD_NC(GPP_D07, NONE),
/* GPP_D08: ISH_UART0_CTS_N_SNSR_HDR */
PAD_CFG_NF(GPP_D08, NONE, DEEP, NF3),
PAD_NC(GPP_D08, NONE),
/* GPP_D09: I2S_MCLK_HDR */
PAD_CFG_NF(GPP_D09, NONE, DEEP, NF1),
/* GPP_D10: HDA_BCLK (HDR) */
@ -261,8 +247,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_F20, NONE, DEEP),
/* GPP_F22: THC1_SPI2_DSYNC */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
/* GPP_F23: SMC_LID */
PAD_CFG_GPI_SCI_LOW(GPP_F23, NONE, DEEP, LEVEL),
/* GPP_H */
/* GPP_H00: NC */
@ -292,9 +276,9 @@ static const struct pad_config gpio_table[] = {
/* GPP_H13: CPU_C10_GATE_N_R */
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
/* GPP_H14: ISH_I3C1_SDA_SNSR_HDR */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_H14, NONE, DEEP, NF4),
PAD_NC(GPP_H14, NONE),
/* GPP_H15: ISH_I3C1_SCL_SNSR_HDR */
PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_H15, NONE, DEEP, NF4),
PAD_NC(GPP_H15, NONE),
/* GPP_H17: MIC MUTE LED */
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
/* GPP_H18: GEN4_SSD_PWREN */