mb/hp/snb_ivb_desktops: Add Compaq Pro 6300 MT/SFF variant
A compaq_8300_elite_sff build can run on these models mostly unmodified. Spawn a new variant from it, tie up some obvious loose ends and bring it officially into the fold. BUG=https://ticket.coreboot.org/issues/581 Change-Id: Ic0f04d586a8361968d7f6c3e3d048f945528cb84 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Walter Sonius <walterav1984@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Keith Hui
Felix Singer
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109
Documentation/mainboard/hp/compaq_pro_6300_series.md
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109
Documentation/mainboard/hp/compaq_pro_6300_series.md
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@ -0,0 +1,109 @@
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# HP Compaq Pro 6300 Series
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This page describes how to run coreboot on the HP [Compaq Pro 6300 Series] desktop.
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These come in two versions: Microtower or Small Form Factor (SFF). They share the same
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mainboard (657239-001) and Maintenance and Service Guide (690362-003/c04034127). This port has
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been tested on a SFF unit.
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## Working
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- i3-3220 / e3-1225v2 CPUs
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- SeaBIOS (version rel-1.16.3-0-ga6ed6b70)
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- EDK2 (MrChromebox/2502)
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- Fedora-mate with Linux kernels 6.11.4, 6.13.6; KDE neon with Linux kernel 6.8.0 / 6.11.0
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- Mixed memory configurations from single 4GB to 24GB total with 1.35v & 1.5v modules
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- Integrated Ethernet
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- Serial port
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- PS/2 keyboard and mouse
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- Integrated graphics over DisplayPort and VGA port
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- libgfxinit textmode (SeaBIOS) / framebuffer (EDK2)
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- discrete GPU's show boot screen using SeaBIOS / EDK2 (LOAD_OPTION_ROMS=TRUE)
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- All SATA ports
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- All USB2 & USB3 ports
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- PCI slot (Realtek RTL8169 GbE card)
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- PCIe 3.0 x16 using 2.0 8x 10Gb Intel X540-AT2 / 1.0 16x nVidia GeForce(6200 LE / GT640-2GD3)
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- PCIe 2.0 x1 using 2.0 1x 2.5Gb Realtek RTL8125
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- PCIe 2.0 x1 using 1.0 1x 1Gb Intel 82574L (SeaBIOS loads option rom)
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- Audio built-in speaker (plays music in OS compared to legacy bleep pc-speaker)
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- Front panel audio ports (front headphone port overrides built-in speaker; only microphone
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works with combo mic/headphone with TRRS plug)
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- Back panel audio ports
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- Sensors CPU and 4 DIMM jc42-i2c sensors
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- Booting USB / SATA(HDD/DVD)
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- LEDs HDD, Power(blinks on suspend)
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- Shutdown, Reboot, Suspend & Wake (USB keyboard & LAN)
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- Strip down Intel ME/TXE firmware and hide MEI device
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## Untested
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- Parallel port
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## Not working
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- Simultaneous use of discrete and integrated graphics
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## TODO
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The following things are still missing from this coreboot port:
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- Extended HWM reporting
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- Advanced LED control
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- Advanced power configuration in S3
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## Flashing coreboot
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```{eval-rst}
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+---------------------+------------+
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| Type | Value |
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+=====================+============+
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| Socketed flash | no |
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+---------------------+------------+
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| Model | MT25Q128A |
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+---------------------+------------+
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| Size | 16 MiB |
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+---------------------+------------+
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| In circuit flashing | yes |
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+---------------------+------------+
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| Package | SOIC-16 |
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+---------------------+------------+
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| Write protection | Yes |
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+---------------------+------------+
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| Dual BIOS feature | No |
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+---------------------+------------+
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| Internal flashing | yes |
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+---------------------+------------+
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```
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### Internal programming
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Internal flashing is possible. The SPI flash can be accessed using [flashrom],
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but you have to short the FDO pins located near the rear USB3 ports on the
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motherboard using a jumper to temporarily disable write protections while on the
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stock firmware. Remove the jumper once coreboot is installed.
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### External programming
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External programming with an SPI adapter and [flashrom] does work, but it powers the
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whole southbridge complex. You need to supply enough current through the programming adapter.
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If you want to use a SOIC Pomona test clip, you have to cut the 2nd DRAM DIMM holder,
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as otherwise there's not enough space near the flash.
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## Technology
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```{eval-rst}
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+------------------+--------------------------------------------------+
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| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
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+------------------+--------------------------------------------------+
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| Southbridge | bd82x6x (Q75) |
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+------------------+--------------------------------------------------+
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| CPU | model_206ax |
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+------------------+--------------------------------------------------+
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| SuperIO | Nuvoton NPCD379 |
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+------------------+--------------------------------------------------+
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| EC | |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel ME |
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+------------------+--------------------------------------------------+
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```
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[Compaq Pro 6300 Series]: https://support.hp.com/us-en/product/details/hp-compaq-pro-6300-small-form-factor-pc/model/5232884
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[flashrom]: https://flashrom.org/Flashrom
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@ -140,6 +140,7 @@ GA-H61M-S2PV <gigabyte/ga-h61m-s2pv.md>
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Compaq 8200 Elite SFF <hp/compaq_8200_sff.md>
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Compaq 8300 Elite SFF <hp/compaq_8300_sff.md>
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Compaq Elite 8300 USDT <hp/compaq_8300_usdt.md>
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Compaq Pro 6300 Series Microtower/SFF <hp/compaq_pro_6300_series.md>
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Pro 3x00 Series <hp/pro_3x00_series.md>
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Z220 Workstation SFF <hp/z220_sff.md>
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```
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@ -17,6 +17,11 @@ config BOARD_HP_SNB_IVB_DESKTOPS_COMMON
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select SUPERIO_NUVOTON_NPCD378
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select USE_NATIVE_RAMINIT
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config BOARD_HP_COMPAQ_PRO_6300
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select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
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select BOARD_ROMSIZE_KB_16384
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select SOUTHBRIDGE_INTEL_C216
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config BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
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select BOARD_HP_SNB_IVB_DESKTOPS_COMMON
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select SOUTHBRIDGE_INTEL_BD82X6X
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@ -68,6 +73,7 @@ config MAINBOARD_DIR
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default "hp/snb_ivb_desktops"
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config VARIANT_DIR
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default "compaq_pro_6300" if BOARD_HP_COMPAQ_PRO_6300
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default "compaq_8200_elite_sff" if BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
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default "compaq_8200_elite_usdt" if BOARD_HP_COMPAQ_8200_ELITE_USDT
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default "compaq_8300_elite_sff" if BOARD_HP_COMPAQ_8300_ELITE_SFF
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@ -76,6 +82,7 @@ config VARIANT_DIR
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default "z220_sff_workstation" if BOARD_HP_Z220_SFF_WORKSTATION
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config MAINBOARD_PART_NUMBER
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default "HP Compaq Pro 6300 SFF/MT" if BOARD_HP_COMPAQ_PRO_6300
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default "HP Compaq 8200 Elite SFF PC" if BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
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default "HP Compaq 8200 Elite USDT" if BOARD_HP_COMPAQ_8200_ELITE_USDT
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default "HP Compaq 8300 Elite SFF" if BOARD_HP_COMPAQ_8300_ELITE_SFF
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@ -1,5 +1,8 @@
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## SPDX-License-Identifier: GPL-2.0-only
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config BOARD_HP_COMPAQ_PRO_6300
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bool "Compaq Pro 6300 SFF/MT"
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config BOARD_HP_COMPAQ_8200_ELITE_SFF_PC
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bool "Compaq 8200 Elite SFF"
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@ -0,0 +1,7 @@
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Category: desktop
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Board URL: https://support.hp.com/us-en/product/details/hp-compaq-pro-6300-small-form-factor-pc/model/5232884
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ROM IC: MT25Q128A
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ROM package: SOIC-16
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ROM socketed: no
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Flashrom support: yes
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Release year: 2012
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Binary file not shown.
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@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <superio/nuvoton/npcd378/npcd378.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
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void bootblock_mainboard_early_init(void)
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{
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if (CONFIG(CONSOLE_SERIAL))
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -0,0 +1,17 @@
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-- SPDX-License-Identifier: GPL-2.0-or-later
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with HW.GFX.GMA;
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with HW.GFX.GMA.Display_Probing;
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use HW.GFX.GMA;
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use HW.GFX.GMA.Display_Probing;
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private package GMA.Mainboard is
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ports : constant Port_List :=
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(DP2,
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HDMI2,
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Analog,
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others => Disabled);
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end GMA.Mainboard;
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@ -0,0 +1,176 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO,
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.gpio1 = GPIO_MODE_GPIO,
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.gpio2 = GPIO_MODE_NATIVE,
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.gpio3 = GPIO_MODE_NATIVE,
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.gpio4 = GPIO_MODE_NATIVE,
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.gpio5 = GPIO_MODE_NATIVE,
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.gpio6 = GPIO_MODE_GPIO,
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.gpio7 = GPIO_MODE_GPIO,
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.gpio8 = GPIO_MODE_GPIO,
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.gpio9 = GPIO_MODE_NATIVE,
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.gpio10 = GPIO_MODE_NATIVE,
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.gpio11 = GPIO_MODE_GPIO,
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.gpio12 = GPIO_MODE_NATIVE,
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.gpio13 = GPIO_MODE_GPIO,
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.gpio14 = GPIO_MODE_NATIVE,
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.gpio15 = GPIO_MODE_GPIO,
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.gpio16 = GPIO_MODE_GPIO,
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.gpio17 = GPIO_MODE_GPIO,
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.gpio18 = GPIO_MODE_NATIVE,
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.gpio19 = GPIO_MODE_NATIVE,
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.gpio20 = GPIO_MODE_NATIVE,
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.gpio21 = GPIO_MODE_GPIO,
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.gpio22 = GPIO_MODE_GPIO,
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.gpio23 = GPIO_MODE_NATIVE,
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.gpio24 = GPIO_MODE_GPIO,
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.gpio25 = GPIO_MODE_NATIVE,
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.gpio26 = GPIO_MODE_NATIVE,
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.gpio27 = GPIO_MODE_GPIO,
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.gpio28 = GPIO_MODE_GPIO,
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.gpio29 = GPIO_MODE_GPIO,
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.gpio30 = GPIO_MODE_NATIVE,
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.gpio31 = GPIO_MODE_GPIO,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio0 = GPIO_DIR_INPUT,
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.gpio1 = GPIO_DIR_INPUT,
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.gpio6 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_INPUT,
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.gpio11 = GPIO_DIR_INPUT,
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.gpio13 = GPIO_DIR_INPUT,
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.gpio15 = GPIO_DIR_OUTPUT,
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.gpio16 = GPIO_DIR_INPUT,
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.gpio17 = GPIO_DIR_OUTPUT,
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.gpio21 = GPIO_DIR_INPUT,
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.gpio22 = GPIO_DIR_INPUT,
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.gpio24 = GPIO_DIR_INPUT,
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.gpio27 = GPIO_DIR_INPUT,
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.gpio28 = GPIO_DIR_OUTPUT,
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.gpio29 = GPIO_DIR_OUTPUT,
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.gpio31 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio15 = GPIO_LEVEL_LOW,
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.gpio17 = GPIO_LEVEL_LOW,
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.gpio28 = GPIO_LEVEL_LOW,
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.gpio29 = GPIO_LEVEL_HIGH,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio0 = GPIO_INVERT,
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.gpio1 = GPIO_INVERT,
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.gpio6 = GPIO_INVERT,
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.gpio11 = GPIO_INVERT,
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.gpio13 = GPIO_INVERT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_zero = {
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};
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static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio32 = GPIO_MODE_GPIO,
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.gpio33 = GPIO_MODE_GPIO,
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.gpio34 = GPIO_MODE_GPIO,
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.gpio35 = GPIO_MODE_GPIO,
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.gpio36 = GPIO_MODE_GPIO,
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.gpio37 = GPIO_MODE_GPIO,
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.gpio38 = GPIO_MODE_GPIO,
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.gpio39 = GPIO_MODE_GPIO,
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.gpio40 = GPIO_MODE_NATIVE,
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.gpio41 = GPIO_MODE_NATIVE,
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.gpio42 = GPIO_MODE_NATIVE,
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.gpio43 = GPIO_MODE_GPIO,
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.gpio44 = GPIO_MODE_NATIVE,
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.gpio45 = GPIO_MODE_NATIVE,
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.gpio46 = GPIO_MODE_GPIO,
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.gpio47 = GPIO_MODE_NATIVE,
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.gpio48 = GPIO_MODE_GPIO,
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.gpio49 = GPIO_MODE_GPIO,
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.gpio50 = GPIO_MODE_NATIVE,
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.gpio51 = GPIO_MODE_NATIVE,
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.gpio52 = GPIO_MODE_NATIVE,
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.gpio53 = GPIO_MODE_NATIVE,
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.gpio54 = GPIO_MODE_GPIO,
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.gpio55 = GPIO_MODE_NATIVE,
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.gpio56 = GPIO_MODE_NATIVE,
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.gpio57 = GPIO_MODE_GPIO,
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.gpio58 = GPIO_MODE_NATIVE,
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.gpio59 = GPIO_MODE_NATIVE,
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.gpio60 = GPIO_MODE_NATIVE,
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.gpio61 = GPIO_MODE_GPIO,
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.gpio62 = GPIO_MODE_NATIVE,
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.gpio63 = GPIO_MODE_NATIVE,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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.gpio32 = GPIO_DIR_INPUT,
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.gpio33 = GPIO_DIR_INPUT,
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.gpio34 = GPIO_DIR_INPUT,
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.gpio35 = GPIO_DIR_INPUT,
|
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.gpio36 = GPIO_DIR_INPUT,
|
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.gpio37 = GPIO_DIR_INPUT,
|
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.gpio38 = GPIO_DIR_INPUT,
|
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.gpio39 = GPIO_DIR_INPUT,
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.gpio43 = GPIO_DIR_INPUT,
|
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.gpio46 = GPIO_DIR_INPUT,
|
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.gpio48 = GPIO_DIR_INPUT,
|
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.gpio49 = GPIO_DIR_INPUT,
|
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.gpio54 = GPIO_DIR_INPUT,
|
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.gpio57 = GPIO_DIR_INPUT,
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.gpio61 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set3 pch_gpio_set3_mode = {
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.gpio64 = GPIO_MODE_NATIVE,
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.gpio65 = GPIO_MODE_NATIVE,
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.gpio66 = GPIO_MODE_NATIVE,
|
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.gpio67 = GPIO_MODE_NATIVE,
|
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.gpio68 = GPIO_MODE_GPIO,
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.gpio69 = GPIO_MODE_GPIO,
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.gpio70 = GPIO_MODE_GPIO,
|
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.gpio71 = GPIO_MODE_GPIO,
|
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.gpio72 = GPIO_MODE_GPIO,
|
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.gpio73 = GPIO_MODE_NATIVE,
|
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.gpio74 = GPIO_MODE_NATIVE,
|
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.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio68 = GPIO_DIR_INPUT,
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.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio70 = GPIO_DIR_INPUT,
|
||||
.gpio71 = GPIO_DIR_OUTPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
.gpio71 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
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.direction = &pch_gpio_set1_direction,
|
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.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_zero,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_zero,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
},
|
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.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
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||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
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||||
},
|
||||
};
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||||
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|
@ -0,0 +1,32 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0221, /* Codec Vendor / Device ID: Realtek */
|
||||
0x103c339a, /* Subsystem ID */
|
||||
11, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(0, 0x103c339a),
|
||||
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014020),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x01813c30),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x598301f0),
|
||||
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
|
||||
|
||||
0x80862806, /* Codec Vendor / Device ID: Intel */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
AZALIA_PIN_CFG(3, 0x05, 0x58560010),
|
||||
AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
AZALIA_PIN_CFG(3, 0x07, 0x58560030),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip northbridge/intel/sandybridge
|
||||
device domain 0 on
|
||||
subsystemid 0x103c 0x339a inherit
|
||||
|
||||
chip southbridge/intel/bd82x6x
|
||||
register "sata_port_map" = "0x17"
|
||||
# 0 = Blue
|
||||
# 1 = White #1
|
||||
# 2 = White #2
|
||||
# 3,5 not implemented
|
||||
# 4 = Black (eSATA)
|
||||
register "superspeed_capable_ports" = "0xf"
|
||||
register "xhci_switchable_ports" = "0xf"
|
||||
register "usb_port_config" = "{
|
||||
{1, 0x84b, 0},
|
||||
{1, 0x84b, 0},
|
||||
{1, 0xa4b, 1},
|
||||
{1, 0xa4b, 1},
|
||||
{1, 0xb43, 2},
|
||||
{1, 0x94b, 2},
|
||||
{1, 0x94f, 3},
|
||||
{1, 0xb53, 3},
|
||||
{1, 1, 4},
|
||||
{1, 5, 4},
|
||||
{1, 0x65b, 6},
|
||||
{1, 0x65f, 5},
|
||||
{1, 0x84b, 5},
|
||||
{1, 0x94b, 6},
|
||||
}"
|
||||
|
||||
device ref xhci on end
|
||||
end
|
||||
end
|
||||
end
|
||||
Loading…
Add table
Add a link
Reference in a new issue