drivers/generic/bayhub: Use boolean for power_saving

Change-Id: I7cc89989296b48e20b41e6ff06570a9d30bfc114
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

src/drivers/generic/bayhub/chip.h

@@ -9,8 +9,8 @@
  * Bayhub BG720 PCI to eMMC bridge
  */
 struct drivers_generic_bayhub_config {
-	/* 1 to enable power-saving mode, 0 to disable */
-	int power_saving;
+	/* enable/disable power-saving mode */
+	bool power_saving;
 
 	/* When set, disables programming HS200 mode */
 	bool disable_hs200_mode;

src/mainboard/google/kahlee/variants/baseboard/devicetree.cb

@@ -20,7 +20,7 @@ chip soc/amd/stoneyridge
 		device ref gpp_bridge_1 on end # WLAN
 		device ref gpp_bridge_3 on
 			chip drivers/generic/bayhub
-				register "power_saving" = "1"
+				register "power_saving" = "true"
 				device pci 00.0 on end
 			end
 		end

src/mainboard/google/kahlee/variants/nuwani/overridetree.cb

@@ -40,7 +40,7 @@ chip soc/amd/stoneyridge
 	device domain 0 on
 		device ref gpp_bridge_3 on
 			chip drivers/generic/bayhub
-				register "power_saving" = "1"
+				register "power_saving" = "true"
 				register "vih_tuning_value" = "0x35"
 				device pci 00.0 on end
 			end

src/mainboard/google/kahlee/variants/treeya/overridetree.cb

@@ -40,7 +40,7 @@ chip soc/amd/stoneyridge
 	device domain 0 on
 		device ref gpp_bridge_3 on
 			chip drivers/generic/bayhub
-				register "power_saving" = "1"
+				register "power_saving" = "true"
 				register "vih_tuning_value" = "0x35"
 				device pci 00.0 on end
 			end

src/mainboard/google/sarien/variants/arcada/devicetree.cb

@@ -346,7 +346,7 @@ chip soc/intel/cannonlake
 		device ref pcie_rp13 on
 			# x4 lanes
 			chip drivers/generic/bayhub
-				register "power_saving" = "1"
+				register "power_saving" = "true"
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"

src/mainboard/google/sarien/variants/sarien/devicetree.cb

@@ -372,7 +372,7 @@ chip soc/intel/cannonlake
 		end
 		device ref pcie_rp9 on
 			chip drivers/generic/bayhub
-				register "power_saving" = "1"
+				register "power_saving" = "true"
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
@@ -384,7 +384,7 @@ chip soc/intel/cannonlake
 		device ref pcie_rp13 on
 			# x4 lanes
 			chip drivers/generic/bayhub
-				register "power_saving" = "1"
+				register "power_saving" = "true"
 				device pci 00.0 on end
 			end
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"