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mb/siemens/mc_rpl: Remove unused Type-C data definition

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This mainboard is not going to use Type-C subsystem. Therefore, disable
and remove the config data for it.

Change-Id: I2d9e53bf63b41811040f84cfe9dedf275f1059e4
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88260
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Werner Zeh 2025-07-01 09:00:58 +02:00 • committed by Matt DeVillier
commit 463cda84d2
4 changed files with 0 additions and 47 deletions
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1
src/mainboard/siemens/mc_rpl/Kconfig
View file

@ -16,7 +16,6 @@ config BOARD_SIEMENS_BASEBOARD_MC_RPL
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SOC_INTEL_CSE_LITE_SKU
select USE_SIEMENS_HWILIB

10
src/mainboard/siemens/mc_rpl/devicetree.cb
View file

@ -123,9 +123,6 @@ chip soc/intel/alderlake
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
# TCSS USB3
register "tcss_aux_ori" = "0"
register "s0ix_enable" = "true"
register "dptf_enable" = "true"
@ -311,14 +308,7 @@ chip soc/intel/alderlake
end
device ref pcie4_0 on end
device ref pcie4_1 on end
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp1 on end
device ref tbt_pcie_rp2 on end
device ref tbt_pcie_rp3 on end
device ref crashlog off end
device ref tcss_xhci on end
device ref tcss_dma0 on end
device ref tcss_dma1 on end
device ref xhci on
chip drivers/usb/acpi
register "desc" = ""Root Hub""

1
src/mainboard/siemens/mc_rpl/dsdt.asl
View file

@ -21,7 +21,6 @@ DefinitionBlock(
Device (\_SB.PCI0) {
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/alderlake/acpi/southbridge.asl>
#include <soc/intel/alderlake/acpi/tcss.asl>
}
#if CONFIG(EC_GOOGLE_CHROMEEC)

35
src/mainboard/siemens/mc_rpl/ramstage.c
View file

@ -11,7 +11,6 @@
#include <static.h>
#include <string.h>
#include <drivers/intel/dptf/chip.h>
#include "board_id.h"
#include <intelblocks/power_limit.h>
const struct cpu_power_limits limits[] = {
@ -63,41 +62,7 @@ void variant_update_power_limits(void)
}
}
static const struct typec_aux_bias_pads pad_config = { GPP_E23, GPP_E22 };
static const struct board_id_iom_port_config {
int board_id;
enum typec_port_index port;
} port_config[] = {
{ ADL_P_LP4_1, TYPE_C_PORT_2 },
{ ADL_P_LP4_2, TYPE_C_PORT_2 },
{ ADL_P_DDR4_1, TYPE_C_PORT_2 },
{ ADL_P_DDR4_2, TYPE_C_PORT_2 },
{ ADL_P_LP5_1, TYPE_C_PORT_2 },
{ ADL_P_LP5_2, TYPE_C_PORT_2 },
{ ADL_M_LP4, TYPE_C_PORT_1 },
{ ADL_M_LP5, TYPE_C_PORT_0 },
};
static void variant_update_typec_init_config(void)
{
/* Skip filling aux bias gpio pads for Windows SKUs */
if (!(CONFIG(BOARD_INTEL_ADLRVP_P_EXT_EC) || CONFIG(BOARD_INTEL_ADLRVP_RPL_EXT_EC)))
return;
config_t *config = config_of_soc();
int board_id = get_board_id();
for (int i = 0; i < ARRAY_SIZE(port_config); i++) {
if (board_id != port_config[i].board_id)
continue;
memcpy(&config->typec_aux_bias_pads[port_config[i].port], &pad_config,
sizeof(pad_config));
}
}
void variant_devtree_update(void)
{
variant_update_power_limits();
variant_update_typec_init_config();
}