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mb/lattepanda/mu: Correct UART1 pinmux for native mode

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Correct UART1 TX/RX pad configuration in early_gpio.c from NF2
to NF1. This enables proper UART1 signaling on GPP_D17 and GPP_D18
when operating in native mode.

This change is based on guidance from Intel Doc. No. 648094.

TEST=Patched and booted board. Confirmed UART1 communication
works via serial adapter. Loopback test passed.

Change-Id: Ib1f5ee17e6f3d8a845d024e6b8593606b0430b6f
Signed-off-by: Kun-Yi Chen <kunyi.chen@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88195
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kun-Yi Chen 2025-06-26 00:09:37 +08:00 • committed by Matt DeVillier
commit 26d6da4533
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/lattepanda/mu/early_gpio.c
View file

@ -10,9 +10,9 @@ static const struct pad_config early_uart_gpio_table[] = {
/* UART0 TX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* UART1 RX */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* UART1 TX */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
/* UART2 RX */
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF2),
/* UART2 TX */