PcieRpLtrEnable[] is a boolean, so use true false.
Change-Id: I4b557683b7897487dedfef0bf77e60b0dab9cbcf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86193
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PcieRpEnable[] is a boolean, so use true false instead of 0 1.
Change-Id: I8e67a33f82b7dfa1864016ccd5cd1b7ec119c528
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Add VBT data file for craaskov, and enable its use by selecting
INTEL_GMA_HAVE_VBT.
VBT extracted from stock firmware image Google_Craaskov.15217.616.0;
it has BDB version 2.51, which matches the current FSP binaries.
TEST=build/boot craaskov with edk2 payload
Change-Id: I5854f658b7c8ff421d32b70d43ba8cad94d85b5b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Meteor Lake uses the same helper functon as Alder Lake, so
it can be configured via the opton API.
Change-Id: I6d1dc802e672431aa643e318a7cb045f7d6eaa06
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86239
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an option to selected a reduced brightness for the power LED. The
EC code will use this option to write to the relavant offset
accordingly.
Change-Id: I4796e0572a48bca5f9c59e96466416e975cfe8ca
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This GPIO is only used for SATA SSDs so set it as not
connected.
Change-Id: I42c0ec36eee81a849f744a2d03862797f2463921
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The schematic shows that this GPIO is not connected, so
set it as not connected.
Change-Id: Ia62b76055f839c48fc112ca46d8654db5b331cd9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86236
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On boards that do not use SATA, this should be connected.
For boards that do use it, it should be NF5.
Change-Id: I3115627431e80bd5e0f91b53b80fac7c0c95e6f8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86186
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This value used was just wrong; set the correct one that matches
the verb table.
Change-Id: I400d8a4f8472359e5213a1ce9d51a69cde051098
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Explicitly set ECT in romstage; enable it for boards that use
LPxxx memory and disable it for boards that use SODIMMs.
Change-Id: I41bd9b221dc97bb4f76862f7095c20f4b8bc6036
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Correct, and unify, the configuration of the GPIOs use in ACPI
for enabling and resetting:
* Make all GPIOs host owned
* Set enable GPIOs to DEEP
* Set reset GPIOs to PLTRST
Change-Id: I31b49beeb932d9b59b094dcfe182cfc4d91c2562
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86205
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board does not have TBT 4, so unselect Kconfig values
for it.
Change-Id: Id13bb7fc1f9a8f00c10effeaf4b8e1970a173e36
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These pads are required for Audio Offload, so enable them to match
the configuration in devicetree.
Change-Id: I757b2c2f77edb21d0eb1a59e3e1eb81671b9929f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This board is using the USB interface for Bluetooth so these
can be disabled.
Change-Id: I95c3d1607b62c899acdda6b3b3aae97067e6b266
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
BT_EN (VGPIO_0) needs to be host-owned, so that the driver
can control it during the reset procedure. Adjust it accordingly.
Change-Id: I9acc7943de423c0ab441226c0fb4f437a10d2749
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This GPIO is used as MODEM_CLKREQ, which is Native Function 1.
Adjust the configuration accordingly.
Change-Id: If9db29df2a0da71885556a75abcb1da1508a9308
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is proven to be more reliable when resuming from S3.
Change-Id: I479493a384ae1ca880a0caf255ea832b4bb9a366
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86135
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On PTL RVP, ISH shares UART with FPS, we can enable either ISH UART or
FPS UART, or disable both UART by changing the DIP switch settings. When
DIP switch is not set for ISH, ISH RX signal is disconnected, causing
ISH low power mode failure. Therefore, NC ISH RX pin mux to minimize the
impact on ISH PM. As a result, ISH console won't accept input since this
pin is not connected.
TEST=PTL RVP H1 DB, DIP SW1317 3-6, 4-5 ON to enable FPS UART, ISH main
firmware boots up and runs successfully.
SW1317 all switches OFF to disable both FPS and ISH UART, ISH main
firmware boots up and runs successfully.
Change-Id: Ic84f8ead6a1fd056e649edbb1471bcb913a0a09a
Signed-off-by: Li Feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86005
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This are not used or needed, so remove the configuration for them.
Change-Id: Id422f953dae3157a4ecc61421d246ce1d20019a0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The mass produced boards did not support SATA, so disable it.
Change-Id: I7477b46c929a9d9e0d0351de6146112f78cece9f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These are configured incorrectly, to use the WLAN WAKE GPIOs
as enable GPIOS. Correct these to use WIFI RF KILL, and disconnect
the now unused WLAN WAKE GPIOs.
Change-Id: I12797875acacc231e155ab4e427a950a3b1b9703
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These GPIO's are not used, so disconnect them or set the outputs
low accordingly.
Change-Id: If7eab6e3f6ff94054c0101b794b960626d1df92a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These GPIO's are not used, so disconnect them or set the outputs
low accordingly.
Change-Id: I1fbb43f7081c09848dc80a6ddedfa284a8fcce44
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
These GPIO's are not used, so disconnect them or set the outputs
low accordingly.
Change-Id: I9472e003b730646fea9860d9da960d7f766bdda9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Most users leave the GNA disabled, so adjust the fallback to
match this.
Change-Id: I7779781266a63c8c9f779d25ff2c692bb498c594
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
dptf_enable is a boolean, so use true false instead of 0 1.
Change-Id: I1ab6c6febbafabddd47dc901c9fdeb9327df81b8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86183
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
The google/fatcat board's flash layout was modified to increase the
size of RW_SECTION_A and RW_SECTION_B by 1MB each (from 7MB to 8MB).
The RW_UNUSED region size was reduced to accommodate the increased
RW_SECTION sizes.
This change provides additional space in the RW slots to accommodate
growth in the payload (depthcharge).
TEST=Built and flashed the image. Verified that both RW_SECTION_A and
RW_SECTION_B are populated with the correct firmware components and
that the system boots successfully.
Change-Id: Ie489d53cef00ddc2dc6beef891f870c6bc0562a8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This moves the FPS device from GSPI0A to GSPI0 to align with the
hardware design dated Jan'25.
The FPS device was initially placed on GSPI0A, which was incorrect. This
commit rectifies the configuration by moving it to the correct GSPI0
interface.
This change ensures that the CRFP device is correctly connected and
functions as expected.
BUG=b:377595986
TEST=Able to build and boot google/fatcat.
Change-Id: I3996f1a054204689ad733c650b6f71f1482c0b22
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86143
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Guard the Hyper-Threading option against SOC_INTEL_ALDERLAKE_PCH_N,
as the N200 processors used don't support it.
Change-Id: Ia30a14bd652bf8f2abad5fb5c19aed1cad694929
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86166
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It seems that this is needed for specific drives, specifically,
the WD Black SN770.
Change-Id: Ibade3043489b82e5308231472dfe2c629b591661
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This reverts commit b3718dee9c.
It seems that this is needed for specific drives, specifically,
the WD Black SN770.
Change-Id: I5ac2ea7978fca455d39fc7663e5cb219f3f8746f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
There are no resources to allocate for LDN 0, so drop it to eliminate
a spurious cbmem log error (PNP 4e.00: missing read resources).
Change-Id: I6d9c3982b128e1480bc0948e19825465274dd769
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Currently, the eDP panel has display shift issue. This issue
is caused by too short HS-trail time.
Based on hardware design ANX7625 requires more HS-trail time to
finish mipi data packet decoding before entering LP mode.
So increase HS-trail time to avoid effect of entering LP mode.
da_hs_trail value copy from "kukui/panel_anx7625.c", verified
on corsola.
BUG=b:391304679
BRANCH=corsola
TEST=Display is normal on corsola
Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57
Signed-off-by: Xin Ji <xji@analogix.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86101
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Create the pujjoniru variant of the nissa reference board by copying
the template files to a new directory named for the variant.
And based on schematics PujjoNiru_C5_CHROME_TWL_SCH_MB_V1_1225A.pdf
update devicetree settings.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0)
BUG=b:386221423
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJONIRU
Change-Id: I9265d11caad92548c4b33f36b1795ade0b485de0
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85844
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
These pads are required for Audio Offload, so enable them to match
the configuration in devicetree.
Change-Id: Icbe68adc24c18b089ff1559597bfcb74aead2a60
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86129
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board is using the USB interface for Bluetooth so these
can be disabled.
Change-Id: Iee80595e9e7d0652a723d44b11d9dc7a1c79417a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
BT_EN (VGPIO_0) needs to be host-owned, so that the driver
can control it during the reset procedure. Adjust it accordingly.
Change-Id: I13ac7a31f1518450fc6d8feefb9f37115e4628a6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This GPIO is used as MODEM_CLKREQ, which is Native Function 1.
Adjust the configuration accordingly.
Change-Id: Icc8be62e620a3e51826fb7c2c040da317e7eb470
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86125
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not every board will use CNVi, so move this out of the chipset.cb
and into devicetree.
Change-Id: Ie12e828b2f0a65e46a526746bc06af288270d0d1
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
- Set slow slew rate VCCIA and VCCGT to SLEW_FAST_4
BUG=b:387056119
BRANCH=none
TEST=built firmware and verified by power team, and noise pass.
Change-Id: I57055cdfc9377ba141c620dd4e9301f6e7601629
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86103
Reviewed-by: Dengwu Yu <yudengwu@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
