Configure GPIO (XHCI_INIT_DONE) as output, so that payloads (for example
depthcharge) can assert it to notify EC to enable USB VBUS.
BUG=b:390357201
BRANCH=none
TEST=detect USB devices in depthcharge, and the log is like "Added USB
disk 2."
Change-Id: I99760ace3e87626f55c52dc4f8a30bab27cba345
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Since infracfg.h is not used in pmif_spi.c, remove its inclusion to
prevent build errors in projects that don't have infracfg.h.
BUG=b:379008996
BRANCH=none
TEST=build pass
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I09229ff370a53407b3f0c290704887de367ed80b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87339
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The flickering issue on ATNA40HQ01-0 panel can be resolved by setting
the swing level to the maximum (500mV). Therefore, add FORCE_MAX_SWING
quirk for ATNA40HQ01-0 panel where the fw config's OLED_WQXGA_PLUS field
is set to PRESENT. As OLED_WQXGA_PLUS is currently only available on
Navi, add an overridetree.cb for Navi.
BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
[INFO ] fw_config match found: OLED_WQXGA_PLUS=PRESENT
...
[INFO ] update_swing_preemphasis: Force swing setting to 3 (500 mV)
Change-Id: I4797ef8fe2257a9b578a969794d624d6e0f97d07
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87028
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Enable Acoustic noise mitigation for google/kanix and set slew rate
to 1/8 for IA and GT domains.
BUG=b:409934780
BRANCH=firmware-rex-15709.B
TEST=Able to build and boot to google/kanix
Change-Id: I73460715ac71428843cf505a21de15a6e4d15bea
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87349
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch overrides the FSP-M UART MMIO base address to ensure the FSP
GFX PEIM can output debug console messages when required.
Currently, the default UART MMIO base used by FSP-M/S might not be the
intended console UART for debug output in boot stages, particularly for
the GFX PEIM. By overriding it with the value derived from
`CONFIG_UART_FOR_CONSOLE` when either `PcdSerialDebugLevel` or
`SerialDebugMrcLevel` is non-zero, we ensure that debug logs are
directed to the configured console.
This change is crucial for debugging issues within the GFX PEIM
initialization process.
BUG=b:380375181
TEST=Verified that enabling FSP debug tokens after this change allows
viewing debug output from the GFX PEIM during display initialization.
Steps to reproduce:
1. Flash an AP FW image (`image.fatcat.serial.bin`).
2. Observe the absence of debug output from the GFX PEIM during display
initialization.
3. Dynamically enable the FSP debug token using
```
sudo cbfstool image-fatcat.serial.bin add-int -i 3 -n option/fsp_pcd_debug_level
```
4. Flash the modified AP FW image.
5. Observe debug output from the GFX PEIM during display initialization
```
[INFO]:[IsGraphicsDeviceSupported()]...
[INFO]:[GetVbtStartAddress()]
```
Change-Id: I835ef75cb3046217127823c92f708bfe4f3ff741
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87318
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add the Amston Lake (9W) with MCH_ID 0x4674 to the vr_config table.
Based on Intel docs 721616 rev 2.3.
BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor
Change-Id: I7249d3223ccbb1671a0b84da1c2347737e1aec89
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87246
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
When re-purposing the TCSS port to USB Type-A, PortResetMessageEnable
must be enabled for USB2 ports that are paired with the CPU XHCI port.
Set to USB2_PORT_TYPE_C to enable PortResetMessageEnable.
Also remove the workaround. (workaround CL:87053)
BUG=b:400809281
TEST=Connecting a USB3 speed device,using lsusb -t to check enumerated status.
with change:
/: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/2p, 20000M/x2
|__ Port 2: Dev 2, If 0, Class=Mass Storage, Driver=usb-storage, 5000M
without change:
/: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/12p, 480M
|__ Port 2: Dev 4, If 0, Class=Mass Storage, Driver=usb-storage, 480M
Change-Id: I7c4743d1d3bcf2567fdca9c0e07ed02c240d4baf
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87301
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Stop using magic values and use defines for Global Descriptor Table
(GDT) offsets. Use the existing defines from the corresponding headers.
Change-Id: I40c15f6341bdef9cd457619ec81e7ac624ec2d63
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87254
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A 'quirks' variable is added for panels that require special handling
in the display driver due to sensitivity to the eDP signal quality. The
display driver can then handle the special requests accordingly.
On Navi, the swing level needs to be increased to 3 (500mV) for the
ATNA40HQ01-0 panel to resolve a flickering issue.
BRANCH=rauru
BUG=b:392040003
TEST=check edp training pass and show log:
[INFO ] fw_config match found: OLED_WQXGA_PLUS=PRESENT
...
[INFO ] update_swing_preemphasis: Force swing setting to 3 (500 mV)
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: Ifa8c45050f61d3dff1fa7aed8fa8e435391a6f3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Select RESET_VECTOR_IN_RAM from the common SOC_AMD_COMMON_BLOCK_NONCAR
Kconfig option instead of selecting it in each AMD SoC's Kconfig which
selects SOC_AMD_COMMON_BLOCK_NONCAR.
From family 17h on, the AMD SoCs don't use cache as RAM (CAR) any more.
In most cases, including the coreboot case, the PSP puts coreboot's
bootblock into DRAM, thus RESET_VECTOR_IN_RAM needs to be selected.
There might be a case where the RESET_VECTOR_IN_RAM part isn't true, but
that isn't specific to a SoC generation, so even this unlikely case
doesn't prevent us from moving the selection of the Kconfig option to
the common non-CAR Kconfig option.
Change-Id: I87d7908f94505647f504f9d214e3c52f9c3a3715
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87322
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Re-enable the ISH for uldrenite and set the correct firmware name. ISH
was disabled on uldrenite due to a suspend issue that's no longer
there. Uldrenite PoR is to use the ISH. The issue was caused by a bug
in Intel's Zephyr HAL which included power management logic that
incorrectly handled one of the interrupts.
BUG=b:410645679
TEST=ISH device under lscpi.
# lspci -s 00:12.0 -knn
00:12.0 Serial controller [0700]: Intel Corporation Device [8086:54fc]
Subsystem: Intel Corporation Device [8086:7270]
Kernel driver in use: intel_ish_ipc
Kernel modules: intel_ish_ipc
Change-Id: I567fd43857da0023d063c0bb1b70c206dbee47f4
Signed-off-by: Yuval Peress <peress@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87313
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Move declaration of all CFR objects to a header file, so they don't
need to be guarded. Simplify the enablement of CFR options by creating
board-level Kconfig options as needed.
TEST=build/boot starbook MTL, TGL, ADL-N.
Change-Id: I43dfa6795708e9975b938ce1359629f6b9c4f1cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Use defines to create dxio descriptors as other mainboards.
Change-Id: I09e8a9fc37a7b775b76a3d8e5faaee7828f99000
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87220
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for DPTC by calling SB.DPTC() as part of PNOT().
Change-Id: I29d7177c96217bf03eaea818cfc1f944f4e640a6
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87218
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support memory of SK-hynix H58G56CK8BX146 in mem_parts_used list,
and generate SPD ID for this part.
DRAM Part Name Vendor Model Spec ID to assign
H58G56CK8BX146 SK hynix LPDDR5X 8533 32Gb 6 (0110)
BUG=b:409971450
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go ADL lp5 \
src/mainboard/google/brya/variants/guren/memory/ \
src/mainboard/google/brya/variants/guren/memory/\
mem_parts_used.txt"
Change-Id: I4616b44a164391d7a14cc97efb059e731d35c308
Signed-off-by: Brian Hsu <Brian_Hsu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87275
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Brian Hsu <brian_hsu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
It doesn't cause any problems, because the next line is empty. But it
is wrong nonetheless.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I8f1e99e06575e769f5698e4cd86e44f0b4df8a07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87289
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use GPP_E03 as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.
BUG=b:403383143
Test=emerge-fatcat coreboot and Confirm the log:
cros_ec_lpcs GOOG0004:00: Chrome EC device registered
Change-Id: If7d120fcf2de8dbbbc399d2ead4e294d11ea8a14
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87210
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Because the NIC does not enter ASPM L1.2.
Here we add "enable_aspm_l1_2" in overridetree for RTL8111H.
BUG=b:407469351
TEST=emerge and test with command powerd_dbus_suspend.
Check firmware log output
[INFO ] rtl: Enable ASPM L1.2
Change-Id: I0e4f0a4aba736811f3b803f4a1245a635ec59407
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87232
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The `spi_ctrlr_bus_map` defines the range of SPI bus numbers managed
by different controllers. Previously, the generic `spi_qup_ctrlr`
was hardcoded to manage buses 0 through 15.
Modify the `.bus_end` value for the `spi_qup_ctrlr` entry to be
`QUPV3_SE_MAX - 1`.
TEST=Able to build google/herobrine.
Change-Id: I7e9ec555a6d72d93bc23285e48eab52030978e1a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
APU_I2C*_BASE are defined in the SoC's iomap.h, so include it.
Change-Id: Id7b1674914a045699d6df53b20e35028c3936f67
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87281
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the description of PMC GPIO_CONF register from
EHL EDS Vol 2 Book 2 rev 2.3 #614109.
Some of the groups had incorrect values or even defined
non-existent GPIO groups.
TEST=Boot Protectli VP2420 to Ubuntu 24.04.
Change-Id: I910f3c4c0d31b8d24b83cd2c3a28688b898b5d9f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87050
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
- Update the instructions for building the documentation to account for
the switch from Recommonmark to MyST Parser
- Update outdated URLs
- Update various details to account for the current behavior and
features resulting from previous changes
Change-Id: I569862e30fb88a421ad2338aafabeaf3ea76836a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This reverts commit 4b5a490b6f.
Reason for revert: This effort was apparently given up on since 4 years.
So remove the function, since it is not used at the moment. If someone
wants to bring that effort back to live, said person can feel free to do
so.
Change-Id: I26d5c9fbfd6eae24f876d857a6e952ca0d1a64ae
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This reverts commit 6b446b991b.
Reason for revert: This effort was apparently given up on since 4 years.
So remove the function, since it is not used at the moment. If someone
wants to bring that effort back to live, said person can feel free to do
so.
Change-Id: Ifa1ca58c8bf6aabb5b291d3244b1a1a0a7aec6c7
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87065
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Raptor Lake P specific PCIe root port ID.
Based on intel document 640552 rev 2.81.
BUG=NA
TEST=Customer platform with Raptorlake-P
Change-Id: Ifa7c131b5ae47294c055b9e68dad2764607c032b
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87244
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Several pads were not configured or configured incorrectly. FSP was
correcting them, but adjust the config in coreboot so this is not
necassary.
The config aligns with all other Star Labs boards.
Change-Id: Id41ea5d2f4f4321526d25b27411dad02fbde90b6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87261
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure pads that aren't connected to anything to PAD_NC.
Also, remove comments for these pads.
Change-Id: Iaee9f3fc5639d5147f5bdf45fb5311a0121e2c78
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87260
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure all strap GPIOs as outputs, rather than some being not
connected. This doesn't change anything, but is more explicit.
Set these all to sample on RSMRST.
Change-Id: I944744f103aa2d1c347856a059d3dd6231b219c4
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This updates the Flashmap (FMAP) descriptor to allocate 18MB to
Silicon Management Engine (SI_ME) and 14MB for BIOS. Panther Lake
(PTL) Reference Validation Platform (RVP) coreboot is used with
several types of RVP boards, and this layout with a 14MB BIOS is
very convenient for debugging and creating coreboot for certain
use cases and testing purposes.
TEST=Build the ptlrvp variant (ES) and check if the flashmap of
the coreboot is updated correctly.
Change-Id: Ie85b79ae8f7d4e30cf48eb6301224b0cf01b8dff
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87035
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Intel processor number X7433RE.
Based on docs 721616 rev 2.3.
BUG=NA
TEST=Boots on Intel Alder Lake CRB with X7433RE processor
Change-Id: Ia43945887e7d536b5b7387a4dda4e245973c27ee
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
This patch adds support for the Fintek f81966d SuperIO,
which is very similar to the fintek/f81866d.
Datasheet:
- Name: F81966D/A, Release Date: Oct 2023, Version: V0.21P
BUG=NA
TEST=Customer platform with F81966D, verified with 'superiotool -de'
Change-Id: Ibe3987b6e15eb07b92d7f5a7de2bd511de85e2f7
Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87198
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
The hardware monitor provides access to its address space via the base
address stored in LDN 0x4 at index 0x60/0x61. There is no need to set
the configuration mode here, since the registers in the LDN are not
programmed.
Change-Id: Ic27c9eee5a58727a70fc0ebe60a643f45a418d36
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The HWM port is +5 to the base address stored in LDN 0x4 at index
0x60/0x61. Take this rule into account when configuring the monitor,
as it was done for Fintek SIO chips in the superiotool utility [1].
[1] commit d92745b
TEST=Run coreboot on the motherboard with the Fintek F81966 chip (which
is architecturally compatible) with pnp_write_hwm5_index() in the HWM
initialization code:
- the fans are regulated correctly;
- superiotool prints the values of the configuration registers updated
during initialization.
Change-Id: If39400e56a7d0792a5bc8f312c29dd5e98a0b2d3
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87273
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Harrie Paijmans <hpaijmans@eltan.com>
commit a7eb390796 ("mb/*/*/*.fmd: Start flash at 0")
caused a build failure for all mainboards that generate their FMAP
from the IFD (so intel only) instead of providing one themselves.
Jenkins didn't catch that, because apparently all mainboards that have
the IFD in the 3rdparty/blobs repository provide a custom FMAP.
So there was no defconfig that jenkins tested that would come across
this issue.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ia9852e8ef48148264d2d3f73eb667f3eb8b85005
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87288
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add the AOAC IDs of the I3C controllers. The following documentation was
used to verify this:
Genoa: #55901 Rev 0.40
Mendocino: #57243 Rev 3.08
Rembrandt: #56558 Rev 3.09 (in Mendocino directory)
Phoenix: #57019 Rev 3.09
Glinda: #57254 Rev 3.00
Faegan: #57928 Rev 1.51 (in Glinda directory)
Change-Id: I54d049c58756251506f94d220e1970ccec170918
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87279
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add minimal common AMD I3C controller code that reports the MMIO region
used by the different I3C controllers to the resource allocator. For
this to work, select the introduced SOC_AMD_COMMON_BLOCK_I3C Kconfig
option and add the 'soc_amd_i3c_mmio_ops' device operations to the I3C
device devicetree entries on all SoCs that include I3C controllers.
Change-Id: Iebf709d2548f2535b2a2a03a4f6da9531559c238
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add the base addresses of the I3C controllers and the mmio devices to
the devicetree for the SoCs that have I3C controllers. The following
documentation was used to verify this:
Mendocino: #57243 Rev 3.08
Rembrandt: #56558 Rev 3.09 (in Mendocino directory)
Phoenix: #57019 Rev 3.09
Glinda: #57254 Rev 3.00
Faegan: #57928 Rev 1.51 (in Glinda directory)
For Genoa, those entries already existed in both its iomap.h and its
devicetree. Cezanne and Picasso don't have I3C controllers.
Change-Id: I6e8073e6498266b909b6cc5f589353f2ed23a62f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87276
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST: Tested by entering ACPI S3 sleep state and pressing any key
on USB keyboard wakes up the system.
Change-Id: Ieed635a7199f53c2e7c69c8f17b3ef50b76b8d91
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87287
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make sure that the ROM2 MMIO area starts at flash address 0.
Document 56780
Change-Id: I1fc06517ea496441147375579800f7349e39facc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
When a SPI ROM greater than 16MByte is being used it will be split
into 16MByte chunks that can be remapped in HW as an automatic recovery
mechanism. As an example when the EFS in the first 16MByte is corrupted
and the second 16MByte EFS is valid the HW will switch pages. The automatic
address translation of the MMIO ROM needs to be accounted when accessing
the ROM2/ROM3 BAR.
Add a function to retrieve the current address remapping and print it in
show_spi_speeds_and_modes() for debugging purposes.
Document 56780
Change-Id: I046e029e6135ab57f79b675c62b233203f00d705
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87175
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
