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mb/google/nissa/var/dirks: correct usb2_ports setting

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When re-purposing the TCSS port to USB Type-A, PortResetMessageEnable
must be enabled for USB2 ports that are paired with the CPU XHCI port.
Set to USB2_PORT_TYPE_C to enable PortResetMessageEnable.

Also remove the workaround. (workaround CL:87053)

BUG=b:400809281
TEST=Connecting a USB3 speed device,using lsusb -t to check enumerated status.
with change:
/:  Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/2p, 20000M/x2
    |__ Port 2: Dev 2, If 0, Class=Mass Storage, Driver=usb-storage, 5000M

without change:
/:  Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci_hcd/12p, 480M
    |__ Port 2: Dev 4, If 0, Class=Mass Storage, Driver=usb-storage, 480M

Change-Id: I7c4743d1d3bcf2567fdca9c0e07ed02c240d4baf
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87301
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Ivy Jian 2025-04-14 11:03:08 +08:00 • committed by Matt DeVillier
commit b375a5bbba
2 changed files with 3 additions and 5 deletions
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4
src/mainboard/google/brya/Kconfig
View file

@ -1183,8 +1183,4 @@ config SKIP_RAM_ID_STRAPS
If unsure, leave this option disabled.
config D3COLD_SUPPORT
bool
default n if BOARD_GOOGLE_DIRKS
endif # BOARD_GOOGLE_BRYA_COMMON

4
src/mainboard/google/brya/variants/dirks/overridetree.cb
View file

@ -71,7 +71,9 @@ chip soc/intel/alderlake
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2_A0
# This port is repurposed from Type-C to type-A port.
# Still declare it as Type-C port in order to set PortResetMessageEnable UPD.
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_A0
register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB2_A1
register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" # USB2_A2
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB2_A3