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mb/google/fatcat/var/felino: Use GPP_E03 for EC_SYNC_IRQ

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Use GPP_E03 as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.

BUG=b:403383143
Test=emerge-fatcat coreboot and Confirm the log:
cros_ec_lpcs GOOG0004:00: Chrome EC device registered

Change-Id: If7d120fcf2de8dbbbc399d2ead4e294d11ea8a14
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87210
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
This commit is contained in:
Tongtong Pan 2025-04-08 20:51:10 +08:00 • committed by Matt DeVillier
commit 49a257a7db
2 changed files with 3 additions and 3 deletions
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2
src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
View file

@ -26,7 +26,7 @@
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_F23
#elif CONFIG(BOARD_GOOGLE_FELINO)
#define EC_SYNC_IRQ 0 /* TODO */
#define EC_SYNC_IRQ GPP_E03_IRQ
#define GPIO_PCH_WP 0 /* TODO */
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_D03

4
src/mainboard/google/fatcat/variants/felino/gpio.c
View file

@ -206,8 +206,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_E01, NONE, PLTRST),
/* GPP_E02: NC */
PAD_NC(GPP_E02, NONE),
/* GPP_E03: NC */
PAD_NC(GPP_E03, NONE),
/* GPP_E03: EC_SYNC_IRQ */
PAD_CFG_GPI_APIC(GPP_E03, NONE, PLTRST, LEVEL, INVERT),
/* GPP_E05: NC */
PAD_NC(GPP_E05, NONE),
/* GPP_E06: GPP_E06 */