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mb/google/fatcat/var/felino: fix DMIC1 recording

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According to the PTL GPIO implementation summary document,
NF2 is a null function pin. Correct to NF3 for DMIC_CLK_A1 and
DMIC_DAT_A1 function pins.

BUG=b:378629979
Test=emerge-fatcat coreboot
Verify DMIC recording functionality.
Command: arecord -D hw:0,10 -r 48000 -c 4 -f s32 dmic.wav

Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Change-Id: Ic73b43e6d58376e0c592ef4a1a9c9d9fc7e66928
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
This commit is contained in:
Mac Chiang 2025-04-09 13:44:59 +08:00 • committed by Matt DeVillier
commit 9a3eae088c
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/fatcat/variants/felino/gpio.c
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@ -182,9 +182,9 @@ static const struct pad_config gpio_table[] = {
/* GPP_D15: NC */
PAD_NC(GPP_D15, NONE),
/* GPP_D16: PCH_DMIC_CLK1 */
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3),
/* GPP_D17: PCH_DMIC_DATA1 */
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3),
/* GPP_D18: PCIE_CLKREQ_SD_N */
PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
/* GPP_D19: NC */