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superio/fintek/f81866d: Undo set config mode for HWM

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The hardware monitor provides access to its address space via the base
address stored in LDN 0x4 at index 0x60/0x61. There is no need to set
the configuration mode here, since the registers in the LDN are not
programmed.

Change-Id: Ic27c9eee5a58727a70fc0ebe60a643f45a418d36
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Maxim Polyakov 2025-04-11 09:47:52 +03:00 • committed by Matt DeVillier
commit ace8bb45f7
1 changed files with 0 additions and 4 deletions
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4
src/superio/fintek/f81866d/f81866d_hwm.c
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@ -48,8 +48,6 @@ void f81866d_hwm_init(struct device *dev)
const struct superio_fintek_f81866d_config *reg = dev->chip_info;
u16 port = res->base;
pnp_enter_conf_mode(dev);
/* Use AMD TSI */
pnp_write_hwm5_index(port, HWM_AMD_TSI_ADDR, reg->hwm_amd_tsi_addr);
pnp_write_hwm5_index(port, HWM_AMD_TSI_CONTROL_REG, reg->hwm_amd_tsi_control);
@ -79,6 +77,4 @@ void f81866d_hwm_init(struct device *dev)
/* Set Fan control freq */
pnp_write_hwm5_index(port, HWM_FAN3_CONTROL, reg->hwm_fan3_control);
pnp_write_hwm5_index(port, HWM_FAN2_TEMP_MAP_SEL, reg->hwm_fan2_temp_map_select);
pnp_exit_conf_mode(dev);
}