erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/amd/crater: Enable CPPC support

Browse source 
Enable CPPC configuration in mainboard devicetree.

Change-Id: Ifbe65db23aff932ceb92861426fda9358cd655be
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87217
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ana Carolina Cabral 2025-03-25 09:14:02 -03:00 • committed by Matt DeVillier
commit 24ff10d76e
1 changed files with 8 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

8
src/mainboard/amd/crater/devicetree_renoir.cb
View file

@ -37,6 +37,14 @@ chip soc/amd/cezanne
register "s0ix_enable" = "false"
# CPPC register configuration
register "cppc_ctrl" = "true"
register "cppc_perf_limit_max_range" = "0xFF"
register "cppc_perf_limit_min_range" = "0x00"
register "cppc_epp_max_range" = "0xFF"
register "cppc_epp_min_range" = "0x00"
# general purpose PCIe clock output configuration
register "gpp_clk_config[0]" = "GPP_CLK_ON"
register "gpp_clk_config[1]" = "GPP_CLK_ON"