Instead of open coding what gpio_base2_value() does use the
function to get the GPIO states of the ID pins.
Change-Id: Ib09993998f7e8ee2a7e5295f49ed14058a095eb0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88505
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I8c83b3436818275958cd8eb8b1c0d7b235e0344c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88504
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the custom function to retrieve the value of multiple GPIOs
at once as integer value and use the generic function prototype
defined in include/gpio.h instead.
Therefore:
* select GENERIC_GPIO_LIB
* Stub gpio_input(). Existing code assumes the pin is input.
* Drop get_gpios() implementation
* Include new header file gpio.h
* Migrate pins from type int to gpio_t
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I2296ff72231b569c618295b36b95a89ffebb3a6e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88503
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I714eaf2115a455d327e6b2313dafd0e293bee8a7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In order to use the common gpio.h header file typedef gpio_t in
soc/gpio.h for Intel common code, Intel lynxpoint and Intel broadwell.
Change-Id: I2049a2cfd75c60d00bdd564b294808760b6aff7f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Include the missing header stdbool.h
Fixes compilation error
hybrid_graphics.h:6:28: error: unknown type name 'bool'
while refactoring some code.
Change-Id: I96f7255049cd9e24d74838a173e920a00636b09e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88546
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When moving headers compilation can fail as pmh7.h is missing
the include for type bool. Add the missing include to make sure
future code refactoring works.
Fixed the error:
src/ec/lenovo/pmh7/pmh7.h:27:1: error: unknown type name 'bool'
Change-Id: Ib0a2489a0c461bf021168e98737ecb6062caa696
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rename config options 'USE_DDRx' to 'DRAM_SUPPORT_DDRx' to make them
less clunky, and in preparation to expand their use inside SoC code.
Change-Id: Ie6edd730c5cbad679a90fcf7989a942d9b2dd3d8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <yuchi.chen@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update hda_verb table for pujjocento to optimize noise floor.
BUG=b:433647377
TEST=emerge-nissa sys-boot/coreboot sys-boot/chromeos-bootimage
Verify that the noise floor on AP is less than -90 dB when
DUT plays mute.wav.
Change-Id: Ib8642a88bb707e99c3d459eb70a6fdf5562f4c75
Signed-off-by: lizheng <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88549
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kaladin need to set this config since we use unified firmware for UFS and non UFS skus
BUG=b:432579255
TEST=Flash and boot on every sku on kaladin
Change-Id: I5fa8f51776e6ba13e9003ea7913c2b4784b76217
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88475
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add DRAM part H58G56CK8BX146
BUG=b:432397864
TEST=Flash and boot to OS successfully on kaladin
Change-Id: Id880940d608c76b88e384ee2cbea03eec8e35b53
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88469
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves the shrm_fw_load_reset() API from the SC7280 specific
implementation to the Qualcomm common directory. This change enables
reuse of the API across multiple Qualcomm chipsets.
Change-Id: Ifab870b9aea7396e29fa93c999c29cf11ab0d199
Signed-off-by: Sasirekaa Madhesu <smadhesu@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88545
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set `TPM_TIS_ACPI_INTERRUPT` to 49 (GPE0_DW1_17) for all ocelot
variants using `BOARD_GOOGLE_MODEL_OCELOT` instead of
`BOARD_GOOGLE_OCELOT`.
BUG=b:433177132
TEST=Able to boot Ocelot
Change-Id: I662e1b38530861da008cf54da4a31dd0ac6212c8
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Disable CNVi bluetooth in the baseboard by default. This will be
enabled per variant basis based on the WIFI fw_config in variant.c
file.
BUG=b:433215861
TEST=Able to connect to boot Ocelot and connect to bluetooth.
Below error is not seen when WIFI_PCI_6/7 selected.
```
[ERROR] CNVi BT is enabled without CNVi being enabled
```
Change-Id: Ibe5d22c013852f868a2a3296c79dfdf1de7c1455
Signed-off-by: Pranava Y N <pranavayn@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88551
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The commit introduces changes to support the FATCAT4ES board variant
by updating the EC command range configuration. The changes updates the
gen1_dec register to configure correctly to accomdate the FATCAT4ES
variant which ensures the ec-host communication should not fail. Also it
ensures other conditional checks in the EC header file for enabling this
new variant.
BUG=b:432676108
TEST=Build with the FATCAT4ES configuration and verify ec host
communication is not failing.
Change-Id: I5c84dc2161847f9fe4316c0e63aa876696947423
Signed-off-by: Megha Verma <megha.verma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88552
Reviewed-by: <srinivas.kulkarni@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes redundant touchscreen GPIO configurations from
romstage_gpio_table. These GPIOs are no longer required to be explicitly
set for the touchscreen while using ACPI for touchscreen power
sequencing.
When the generic.use_gpio_for_status flag is enabled, the touchscreen
driver's power resource method will perform a probe to determine the
device's operational status. This probe specifically verifies two
critical conditions:
- The Enable GPIO pin is enabled (HIGH).
- The Reset GPIO pin is not in reset (LOW).
If both of these conditions are met, the touchscreen is considered ready
and functional.
Conversely, if either of these conditions is not met, the _ON method
within the power resource will be invoked. The _ON method is then
responsible for executing the full touchscreen initialization sequence
to bring the device into an operational state.
BUG=b:430444353
TEST=Able to build and boot google/kinmen. Verified touchscreen is
working as expected with this patch.
Change-Id: I0bb2e1ddd4168ef1831b30817dbb3bc3f6e6a5d2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit transitions the touchscreen power sequencing for the Karis
variant from static coreboot GPIO configuration to ACPI-driven
management. This allows the kernel's touch driver to handle the power
sequencing, providing more flexible and dynamic control.
Redundant touchscreen GPIO configurations are removed from
early_gpio_table, and romstage_gpio_table. These GPIOs are no
longer required to be explicitly set in coreboot given the shift to ACPI
power sequencing.
The generic.use_gpio_for_status register is set to true in the
device's override tree to enable ACPI power sequencing for touchscreen
signaling.
When the generic.use_gpio_for_status flag is enabled, the touchscreen
driver's power resource method will perform a probe to determine the
device's operational status. This probe specifically verifies two
critical conditions:
- The Enable GPIO pin is enabled (HIGH).
- The Reset GPIO pin is not in reset (LOW).
If both of these conditions are met, the touchscreen is considered ready
and functional.
Conversely, if either of these conditions is not met, the _ON method
within the power resource will be invoked. The _ON method is then
responsible for executing the full touchscreen initialization sequence
to bring the device into an operational state.
BUG=b:430444353
TEST=Able to build and boot google/kanix. Verified touchscreen is
working as expected with this patch.
Change-Id: I5c049c76fed185a40c31a6e779119c953926e6c9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit transitions the touchscreen power sequencing for the Karis
variant from static coreboot GPIO configuration to ACPI-driven
management. This allows the kernel's touch driver to handle the power
sequencing, providing more flexible and dynamic control.
Redundant touchscreen GPIO configurations in bootblock and romstage are
removed from early_gpio_table, and romstage_gpio_table. These GPIOs are
no longer required to be explicitly set in coreboot given the shift to
ACPI power sequencing.
The generic.use_gpio_for_status register is set to true in the
device's override tree to enable ACPI power sequencing for touchscreen
signaling.
When the generic.use_gpio_for_status flag is enabled, the touchscreen
driver's power resource method will perform a probe to determine the
device's operational status. This probe specifically verifies two
critical conditions:
- The Enable GPIO pin is enabled (HIGH).
- The Reset GPIO pin is not in reset (LOW).
If both of these conditions are met, the touchscreen is considered ready
and functional.
Conversely, if either of these conditions is not met, the _ON method
within the power resource will be invoked. The _ON method is then
responsible for executing the full touchscreen initialization sequence
to bring the device into an operational state.
BUG=b:430444353
TEST=Able to build and boot google/karis. Verified touchscreen is
working as expected with this patch.
Change-Id: I967650290dda9ca3ca66a2f161fff0ae84b14f04
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88516
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8189 uses MT6359 clk_buf, and will use new RC mode with srclken_rc.
The clk_buf will provide several 26M clocks, and these clocks can be
independently turned on.
BUG=b:379008996,b:422503190,b:403478729
BRANCH=none
TEST=show driver init log:
RG_CENTRAL_CFG1: 0x104014e5
RG_CENTRAL_CFG2: 0x1010
RG_CENTRAL_CFG3: 0x400f
Signed-off-by: LiLiang Chen <liliang.chen@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ia04526d55191c695caf3ef40002e1ec99f299966
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88525
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces support for asynchronous coreboot File
System (CBFS) file loading from SPINOR, specifically targeting the
fsps.bin file, in the Intel Panther Lake (PTL) System on a Chip (SoC)
platform. The primary motivation for this change is to improve boot time
performance by utilizing SPI Direct Memory Access (DMA) to preload files
while the Central Processing Unit (CPU) continues executing other tasks.
This feature uses cooperative multithreading. Because the scheduling is
cooperative, the boot process stays mostly predictable, which minimizes
debugging difficulties while still enhancing boot performance.
The preload operations are strategically modified according to the
chipset lockdown settings. This guarantees that payload preloading is
finalized prior to SPI DMA locking when the chipset lockdown is managed
by FSP or otherwise maximizes the pre-loading feature.
Note: As there is no UPD to control the Fast DMI DMA interface lockdown,
a special FSP binary, built without the Fast SPI DMA driver
(PcdSpiDmaEnable), is required when chipset lockdown setting is set to
CHIPSET_LOCKDOWN_COREBOOT.
TEST=On a Fatcat device, with CHIPSET_LOCKDOWN_COREBOOT, the boot time
has improved by around 17-18 ms.
Change-Id: I4106058d382b99eac5f988c134cc02f024f7d473
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88300
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit implements a token-based queuing system to reduce delays
between consecutive DMA operations. The queuing mechanism aims to
improve overall throughput.
A Kconfig option FAST_SPI_DMA_QUEUE_SIZE defines the maximum number of
concurrent DMA transfers that can be queued and processed.
When DMA transfers are queued, a new thread is initiated to run
fast_spi_dma_main_thread(). This function consistently monitors for
available transfer tokens and performs DMA operations when tokens are in
the DMA_REQUESTED state. If there are no tokens in the desired state,
the thread_running flag is set to false, and the thread terminates
smoothly.
While it provides a barely perceptible boot time improvement with the
Panther Lake configuration, it makes the boot flow more consistent and
predictable.
TEST=On a Fatcat device with CBFS_PRELOAD enabled and set up, we observe
consecutive logs as follows, proving a new DMA transfer is issued
as soon as the previous one's completion is detected.
[DEBUG] Fast-SPI: transfer completed in 2574 us
[DEBUG] Fast-SPI: Reading 240 blocks via DMA
Change-Id: Ic5249362041cfa028885874b43893e1d7942ed94
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
In PTL Crashlog Watcher interface is used instead of Mailbox since it
is based on the Intel Platform Monitoring Technology (PMT) standard.
The Watcher interface provides a more flexible and efficient way to
control and monitor crashlog collection. Hence the functionalities like
rearm and clear are implemented using watcher interface instead of BIOS
mailbox to PUNIT.
Change-Id: I24c5c9753a577b255a7129d20ab83f93001a0485
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88500
Reviewed-by: <srinivas.kulkarni@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
After the BIOS reads and processes the crashLog record, it sets the
CONSUMED_BIOS bit to indicate that the reading and storing of crashlog
record is complete. This is read only bit. When this bit is set ,
crashlog discovery and data collection are skipped. This bit helps in
preventing the same crashLog from being extracted multiple times after
a reset.
BUG= b:None
TEST= The header value during warm boot after crash
cpu_cl_disc_tab.header.data dw0=88420003, dw1=0x0
Change-Id: I4b9e6900218f28b6beb71b7667bc1c57f0134a84
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88499
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
This patch refactors the BMP rendering logic, moving it from
drivers/intel/fsp2_0 to src/lib. This centralizes the code
responsible for rendering BMP images to the framebuffer.
Key changes:
- Move BMP rendering functions (e.g., calculate_logo_coordinates,
copy_logo_to_framebuffer) and their dependencies to
src/lib/render_bmp.c and src/lib/render_bmp.h.
- Decouple BMP definitions from UEFI headers by introducing new
coreboot-specific structures for BMP images and BLT pixels.
- Consolidate bootsplash-related declarations into bootsplash.h,
including new `fw_splash_vertical_alignment`,
`fw_splash_horizontal_alignment`, and `struct logo_config`.
- Update `soc_load_logo_by_coreboot` to use the new common
`load_and_render_logo_to_framebuffer` function and `struct
logo_config` for rendering.
- Relocate `release_logo` to `src/lib/render_bmp.c` for better
module structure.
- Update `src/lib/Makefile.mk` to include the new render_bmp.c.
This refactoring improves code organization and reusability, making
BMP rendering accessible without tight coupling to Intel-specific
driver code.
BUG=b:427387842
TEST=Verify firmware splash screen on google/fatcat.
Change-Id: I0e20ea7e44b4b3ccdb2d4aa9b6aa10ed3447ccfc
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88361
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add wifi SAR table support for kinmen. Bit 2 in the CBI/FW_CONFIG
field is used to determine which SAR table file to load at runtime.
BUG=b:424628935
TEST= check coreboot log:
before:
[WARN ] CBFS: 'wifi_sar_defaults.hex' not found.
[ERROR] Failed to get the wifi_sar_defaults.hex file size!
[ERROR] failed getting SAR limits!
after:
[INFO ] Use wifi_sar_0.hex.
[INFO ] CBFS: Found 'wifi_sar_0.hex' @0x7072c0 size 0x116 in mcache @0x73abdd28
Change-Id: I63e44ba0a4094264165cc9bd7e41c4bd2094c242
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This change adds the necessary configuration for the parade
touchscreen (PRT3406) device, connected to I2C bus 24.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:431658711
TEST=emerge-nissa coreboot and parade touchscreen can work well
Change-Id: I5ca4853c4105d422b907c29fd0b3a4f2a1ce6d9f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Fix resume failure on i2c-ILTK0001:00 where acpi_subsys_resume
returns -121. Increase reset_delay_ms from 10ms to 100ms to
ensure the device is ready after reset.
BUG=b:411164455
TEST=Build and boot and verified resume time across 5 cycles.
All within 500 ms limit.
Suspend-resume time w/ and w/o:
w/o: Average=433.6 ms
1. Resume time 430 ms within limit of 500 ms
2. Resume time 435 ms within limit of 500 ms
3. Resume time 440 ms within limit of 500 ms
4. Resume time 430 ms within limit of 500 ms
5. Resume time 433 ms within limit of 500 ms
w/: Average=449.4 ms
1. Resume time 440 ms within limit of 500 ms
2. Resume time 439 ms within limit of 500 ms
3. Resume time 451 ms within limit of 500 ms
4. Resume time 482 ms within limit of 500 ms
5. Resume time 435 ms within limit of 500 ms
Change-Id: I67ea9aa5ca8ba6f30f772c2decd464d889865347
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88527
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Because when stylus bringing into the garage will resume
from suspend using powerd_dbus_suspend command, so
update the stylus setting which wake_gpe from DW0 to DW2
to fix the funtion.
BUG=b:430712526
BRANCH=none
TEST= Build and boot to OS and check when stylus bringing into
garage and the system will not resume from suspend.
Change-Id: I526b608b03631f365bb33fc44904c87b00a47436
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88479
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Before, the I2C/I3C pads could only be configured to I2C mode. To be
able to use the I3C controller, add the corresponding options and
implementation for the I3C pad mode with all possible voltages.
Change-Id: I1cc2e830019101cfef96b9474477717a8a75111c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This patch supports wake on touch for touchpad when LPSS I2C interface
is used by overriding GPE DW0 with group GPP_F.
Schematic version: schematic_1433518
Platform Mapping Document : Rev0p86
BUG=b:394208231
TEST= Build Ocelot and verify it compiles without any error.
Change-Id: Id2cc248aacebc0e85d06ad5c63c0605dd72cd05c
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Avi Uday <aviuday@google.com>
Since the boot flow is different on AMD compared to other x86
platforms document what is done and where.
Explain that AMDCOMPRESS does more than compressing the input.
It also parses the input as an ELF and extracts the first PT_LOAD marked
area from it and discards all other information from the ELF.
Explain bootblock.bin generation and that it has not much to do
with bootblock.elf, unlike on other platforms.
While on it also fix a whitespace in the following line.
Change-Id: Ida763f879c133be54ea1ca2abd3059db0d2c1ef7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87316
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Ensure that only one PT_LOAD segment is inside the input ELF as
the tool only expects and support one PT_LOAD segment. Instead of silently
discarding all other PT_LOAD segments than the first throw an error.
Change-Id: I90cfc8b9dd0b5e8060880790e5ff0ce73843943b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87315
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently we set DP_PHY_DIG_TX_CTL_0 during the PHYD reset flow.
However, that would cause the training to fail and result in
intermittent black screen issues.
As suggested by the eDP PHYD designer, the reset procedure should be
refined by setting bit 0 of DP_PHY_DIG_SW_RST from 0 to 1 to reset the
eDP PHYD status before training. DP_PHY_DIG_TX_CTL_0 controls the eDP
PHYD lane count: setting BIT0 enables lane0, and setting BIT1 enables
lane1. The eDP PHYD designer also recommends that when resetting PHYD,
it is sufficient to set DP_GLB_SW_RST_PHYD and leave DP_PHY_DIG_TX_CTL_0
unchanged.
After this change, this function is identical to the mt8189
implementation. Move dptx_hal_phyd_reset code to common for reuse.
BUG=b:427119942
BRANCH:rauru
TEST=Check the display function on Navi
Change-Id: I07bd6203a2b957eea79d1431953b043820c00338
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88450
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a DMA lock mechanism to secure the Fast SPI DMA operations
during the payload boot phase. A new `fast_spi_dma_lock` function is
added to lock the DMA control register when the system enters the
payload boot state. This ensures that DMA operations are appropriately
secured, preventing any unintended data transfers post-boot.
TEST=On a Fatcat device with an FSP not locking down Fast SPI DMA,
coreboot logs show "Fast-SPI: DMA has been locked." and
/sys/devices/pci0000:00/0000:00:1f.5/config shows that bit 15 of
register FAST_SPI_DMA_CONTROL (0xbc) has been is set.
Change-Id: Ie4abbcfc798480319a32b0049e3559d623ef78ef
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88488
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix Type C USB and display function
BUG=b:429267772
TEST=Build and flash to DUT, verify Type C USB and display function works
Change-Id: I37af5f4608b2756f0918a6b544b53818d1e45d63
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88374
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the introduction of the stack canary breakpoint QEMU uncovered
a different bug within coreboot. Currently the compiler optimizes
over aggressively inline functions and memory stores.
That also affects write_at_ble8(), which is supposed to store a
single byte at time. The compiler however optimizes multiple byte
stores into a single wider (and possibly unaligned) store operation.
This can be seen in the emited assembly code of write_le16(), as used
to install the EBDA:
401348a: 66 c7 04 25 13 04 00 movw $0x400,0x413
4013491: 00 00 04
Make sure that the compiler does not optimize multiple calls to
write_at_ble8() by adding the volatile qualifier.
The emitted assembly code of the same function changes to:
401394c: c6 04 25 13 04 00 00 movb $0x0,0x413
4013953: 00
4013954: c6 04 25 14 04 00 00 movb $0x4,0x414
401395b: 04
Fixes a strange bug in QEMU where it triggers the DEBUG breakpoint
handler on unaligned 16-bit stores in the first 4KiB of memory.
Aligned stores and store outside of the first 4KiB do not dispatch
the DEBUG breakpoint handler.
Change-Id: Ibbc661235a38c7f7540b656a67f067c3e51105d1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use microcode updates from intel-microcode submodule by default.
Downstream users can still decide to use their own files.
TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/beechnutcity CRB
Change-Id: I5a37423426b19dc9ec76984df5ad9c6d2a28f83b
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
IBL shall use PMC device to program ABASE instead of PCR.
TESTED=Build and boot on intel/avenuecity CRB with below log:
[INFO ] soc_config_acpibase : pmbase = 501
Change-Id: I3497c287a5370deed02b269405bc45d5d41e7f33
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88144
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If fit_table_entries() fails, it returns zero, but the sort loop
subtracts 1 from that value before comparing for the loop termination.
Since the value is unsigned, this results in wraparound overflow,
effectively causing an infinite loop. To mitigate this, store the
number of FIT entries as an int, and use that for the loop exit
condition check. Use int type for the loop counters as well to
avoid the compiler complaining about an signed/unsigned comparison.
BUG=CID 1612099
Change-Id: Id0a16bdb86d075ec6c322b44fd782f81d15ca6a7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88324
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Recent development of the "pro_6300" variant fixed VGA output in EDK2
(MrChromebox/2502) and SeaBIOS 1.16.3 using libgfxinit by removing the
following line from Kconfig "select GFX_GMA_ANALOG_I2C_HDMI_B" hinted by
Keith Hui. This fix also applies to the "compaq_8300_elite_sff" variant.
The VGA output without this change only works after loading the OS!
Change-Id: Ifaf3df12fdde996d2842650be411a6d844f949a4
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
