Halfway through the review of CB:89493 (commit 6e45016610 ("intel
soc,southbridge: Add Kconfig to set TSBS in IFD during build")) the
option was renamed and lost "CONFIG_" prefix in the Makefile. Add the
missing prefix.
The omission was discovered and the fix tested while trying to use this
option on Protectli VP6670 where incorrect Top Swap size prevented a
boot.
Adding a missing space while at it.
Change-Id: Ie85fc0b81b2231760878306cf065598bec390e9f
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90432
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To modify the Top Swap Block Size in the FD (if provided and
CONFIG_HAVE_IFD_BIN=y), set the following Kconfig variables:
- CONFIG_INTEL_HAS_TOP_SWAP
- CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
- CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE
- CONFIG_INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE
Needed for the bootblock redundancy feature suggested at
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
TEST=build VP66xx with custom Kconfig, check if TSBS is modified in FD
Change-Id: I94d3d3e2511a7e56392a9e34f845ae91602ce7f1
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89493
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Check if CPU has been replaced before doing ram init. When it
has been replaced disable MRC cache and do a full memory training.
Also use get_us_since_boot() to skip waiting additional 50msec
when not necessary. Setting up NEM in bootblock is so slow that
50msec might already have passed.
Before:
940:waiting for ME acknowledgment of raminit 116,514 (62,804)
After:
940:waiting for ME acknowledgment of raminit 68,708 (7,211)
Boots 48msec faster than before.
Change-Id: I2d9729792c3546dc9bf23192c42619cd7d639d1c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88794
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rewrite suspicious register handling as per reference code. Proper
handling of the value in the RPC register needs some IOBP operations,
and will be done in a follow-up once `pch_iobp_update` can be used.
TEST=Still boots on Lenovo X220.
Change-Id: I7cf8851e98e3971593734dc2a46f7e0b43d8cdca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Use udelay() over reading port 80h to delay CPU operation.
Since SMBUS runs at 100Khz a typical operation takes about
200usec or more to complete. Using udelay(1) doesn't delay
the boot for too long.
TEST=Booted on Lenovo X220. No additional boot delay was found.
Change-Id: Ied745927b1c54b53d7450b8e0c0a03d648a3ebba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88810
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move ICH7 GPIO register defines into private scope. This enforces
the use of GPIO common code and mainboard can no longer directly
access GPIO I/O registers.
Change-Id: Iedf3e55f8aecf7b1ac6f47b29d9f88d58d1b6867
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Introduce a new helper function to set the INVERT bits on
the first GPIO bank. Use it on google link instead of using
a custom implementation.
Change-Id: Icfdbc3dcae5678695b6fcc9dab7ff97d291963cd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88565
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement the two functions defined as prototypes in gpio.h.
Allows to drop custom SMI handler code and use the generic function
from gpio.c instead.
Change-Id: I795af83374118d3fc2b46837b1822205c966fda6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88508
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I8c83b3436818275958cd8eb8b1c0d7b235e0344c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88504
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the custom function to retrieve the value of multiple GPIOs
at once as integer value and use the generic function prototype
defined in include/gpio.h instead.
Therefore:
* select GENERIC_GPIO_LIB
* Stub gpio_input(). Existing code assumes the pin is input.
* Drop get_gpios() implementation
* Include new header file gpio.h
* Migrate pins from type int to gpio_t
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I2296ff72231b569c618295b36b95a89ffebb3a6e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88503
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the custom function to set the value of a single GPIO and
use the generic function prototype defined in include/gpio.h instead.
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I714eaf2115a455d327e6b2313dafd0e293bee8a7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In order to use the common gpio.h header file typedef gpio_t in
soc/gpio.h for Intel common code, Intel lynxpoint and Intel broadwell.
Change-Id: I2049a2cfd75c60d00bdd564b294808760b6aff7f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
coreboot's method of creating IFWI is to modify an existing IFWI
images by deleting the IBB, replacing the IBBL with the bootblock
and everything else is put in the OBB.
This poses a problem when using Intel's FIT or technologies such
as Boot Guard. The main problem is that the IBB is never verified by
the CSE or copied from SRAM to CAR, so the CSE cannot complete BUP
and stays in recovery mode. The vast majority of the stages in
Apollolake's Secure Boot flow is not met using this method (Intel
document number 597827 summarizes these steps).
This patch series is based on the principles of a patch from Brenton
Dong (CB:17064) creates an IBBL, IBB and OBB binaries with the
correct functions to complete the Secure Boot flow. This is to copy
the IBB from SRAM using the CSE's Ring Buffer Protocol.
These binaries can then be used by FIT or coreboot's existing
method of hacking IFWI together (IFWI_STITCH) via IFWITOOL. If it is
the latter and Boot Guard is enabled, the hashes for IFWI and "ibb+obb"
must be recreated.
Whilst this option doesn't form a complete image, the components it
builds will work as Intel intended them to once stitched correctly into
an IFWI image.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0deebf04f22f3017ee0c13bf1ca7f6dcc0d458b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
TEST=build/boot google/panther with CFR options enabled.
Change-Id: I5067e7a69f1f53f0f93d337198d3c349facec086
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add an option variable 'me_disable' to control the visibility of the
HECI PCI device at runtime. Default to the Kconfig selection if not set.
Change-Id: I12c4c9f062cb5904c2f9c05b333bf0ed81aba632
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87384
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a header with CFR objects for existing configuration options,
so that supported boards can make use of them without duplication.
TEST=build/boot samsung/stumpy with CFR options enabled.
Change-Id: Ia6906992deb948869ecfd8a5f6fc3883220811ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Two ME current working state definitions are missing. They are
needed for CB:85413. Get them from intelmetool.
Change-Id: Ie163c4b29155e3fd44f0cb3096f825c84da37559
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87394
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that we require the FMAP to start at offset 0 in the flash, we can
assume this across the entire codebase and therefore simplify it on
several ends.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ieb1a23f9c0ae8c0e1c91287d7eb6f7f0abbf0c2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86771
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This is now drawn (indirectly) from main usb_port_config.
Also drop it from autoport.
Change-Id: I8c5e9b2016cf56538de06575181a0a6b738c6a28
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85925
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pch_is_lp() returns CONFIG(INTEL_LYNXPOINT_LP) which is a boolean,
so use boolean instead of int.
Change-Id: Ic7bf801f549077cbd493e0a53ba7eff7a72728fb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84859
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As xHCI ports 1-4 and OC pins 0-3 are all shared with EHCI,
xhci_overcurrent_mapping should never deviate from the USB 2 (EHCI)
overcurrent mapping specified in the USB port config in the devicetree.
Get the mapping from EHCI and free mainboards from specifying
it separately.
A Ghidra inspection of MRC binary indicates it is doing the same.
After this patch xhci_overcurrent_mapping becomes redundant and
will be removed in a follow-up.
Change-Id: Iab30a07c8df223e4053c5f28df5e5ed926f278f7
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Since commit 64d9e85681
("cpu/x86/smm_module_hander: Set up a save state map"), the
smm_get_save_state() function can return a NULL pointer. Therefore, it
is crucial to ensure that code properly handles the potential for a
NULL pointer return value from smm_get_save_state().
Change-Id: Ie263393ca7d9d6b5e9868c5f73240fc788116cd0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
These header files do not seem to be used in coreboot. Presumably
they're left over after the code that used them was removed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ide70239c7c2e93fff548d989735450396308c62b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85370
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Remove <assert.h> when it is not used.
Change-Id: Icb8ee7dcfd05e0a3131d02d1bc8fe150bbf9527b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85164
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add a scope parameter for `intel_write_pci0_PRT()` so that it could be
reused for multiple domains.
Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85013
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
As per commit 8651731537 ("sconfig: Move config_of_soc from device.h
to static.h") and commit 05a13e7ed9 ("sconfig: Move (WEAK_)DEV_PTR
from device.h to static.h"), sources that use code generated from the
devicetree should directly include static.h. This allows static.h to be
removed from device.h, eliminating many unnecessary dependencies on the
devicetree for objects that only need the device types and function
declarations.
Add static.h to the includes of all remaining files that require static
devicetree access through config_of_soc(), the sconfig generated names,
or DEV_PTR().
Change-Id: I1d35ff2ac22f9ff5e0aa38b7ad707619e50387f3
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84591
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and
`ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include
`SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`.
This allows these features to be enabled even when CSE sync is performed
in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU`
config is enabled).
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Allows to use this driver for the SMBus console without sending an index
byte for every sent char (i.e. !CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER).
Tested with WiP VIA CX700-M2 port and FT4222H as receiver.
Change-Id: Ic368ef379039b104064c9a91474b188646388dd2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82763
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 88decca14f ("ACPI: Add helper fill_fadt_extended_pm_io()")
moved the population of the extended FADT to a separate function, but
incorrectly placed that function call before various length fields were
populated, leading to spurious validation errors in the cbmem boot log.
Correct this by moving the call to fill_fadt_extended_pm_io() after
the required fields are populated.
TEST=build/boot google/slippy (wolf), verify no FADT errors in cbmem
console log.
Change-Id: I1f8522e4813e6071692206f2b7ad2a2f5086071e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83035
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Looks like PCIe root port device IDs for 9-series PCH-H are missing from
commit 434d7d4582 (sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHs)
for some reason. Add them, so that coreboot performs PCIe initialisation
for 9-series PCH-H.
Change-Id: I1589418e5e25daabbf09c66c637e9c4f86aa02a6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82947
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove USB configurations and data structures from northbridge
devicetree (SNB+MRC boards) and bootblock/romstage C code
(native-only SNB boards). All USB configurations are drawn from
southbridge devicetree going forward.
Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Transfer all USB responsibilities to southbridge/intel/bd82x6x,
using one set of USB port configuration supplied by mainboards
in the southbridge section of their devicetree.
For MRC raminit, export southbridge_fill_pei_data() as a hook for
southbridge code to implement. With new code via this hook, bd82x6x
fills pei_data based on this one set of USB port config.
For native raminit, early_usb_init() now goes directly to the devicetree
and no longer get passed an address to it.
TEST=abuild passes for all affected boards. All USB ports still work
on asus/p8x7x-series/v/p8z77-m.
Change-Id: I38378c7ee0701abc434b030dd97873f2af63e6b0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81881
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace 3 unused values in the map with those found during a Ghidra
examination of MRC binary, and on hardwares running vendor firmware
(asus/p8z77-m and HP Z210 CMT Workstation).
The outgoing values were introduced in commit 216ad2170c
("sb/intel/bd82x6x: Add new USB currents") in anticipation for
Gigabyte GA-Z77-DS3H mainboard, but effort to land it was eventually
abandoned. Since commit xxxxxxxxxxxx, such values can be placed
directly in the port config, so there should be no hurdle should that
effort be resurrected.
Add a few #defines in pch.h to place some inline documentation
on MRC values, but more will be documented in the future when this
mapping is introduced MRC-side.
Finally, update autoport to match.
Change-Id: I195c7f627994e48f7a6e6698589504dc96248cff
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This is the first step to:
- Move USB port configs, which are static, from C code to devicetree;
- Unify USB port configs between MRC and native code path.
Change-Id: I59af466d41790e2163342cac8676457ac19371ea
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81878
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For USB to work under native code path, the USB port config needs to
include a current setting for each port, which gets mapped to an
initialization value that gets programmed into the USBIRx register
for the respective port. This map resides in early_usb.c.
The need to update it, whenever we see a previously unaccounted for
initialization value, is getting out of hand.
Instead this patch will allow specifying those values, presumably
taken from an inteltool dump while running vendor firmware,
directly in the USB port map.
Because all USBIRx values are always in the 0x20000yyy form, we only
need the lowest 12 bits. We have more than enough space in the USB
port config structure for this.
As the lowest yyy value we saw so far is 0x53, a note is included to
limit the map to not more than 80 entries. Any value that is too big
to be an index into the map is programmed directly, + 0x20000000, into
the registers.
This opens the future possibility to use the map for a simpler
mapping for boards also using MRC, and remove the need for any
mapping at all for the rest.
Change-Id: I3d79b33bac742faa9bd4fc9852aff73fe326de4e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This reverts commit b3db3abd63.
Reason for revert: `Wcalloc-transposed-args` is new command option came with GCC-14. older versions will not support it.
Change-Id: I74ef8de1f7d38e1e0519c3b41e79fd9b11d8e16f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82759
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<stdio.h> header is used for input/output operations (such as printf,
scanf, fopen, etc.). Although some input/output functions can manipulate
strings, they do not need to directly include <string.h> because they
are declared independently.
Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GCC-14 documentation says "The first argument to calloc is documented to
be number of elements in array, while the second argument is size of
each element, so calloc(n, sizeof (int)) is preferred over
calloc(sizeof(int), n)."
Change-Id: I77b6f4d2eda487b087ba5665b588999633c33e8d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82658
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allowing access to change GPIO configuration from ACPI is asking
for trouble. Kill it while nobody cares (yet).
Access to mainpulate and blink GPIOs is maintained.
Change-Id: Id80a7e2f815a58750623c133bb30e5ed84a6e2ed
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Break out the individual bits of GPIO blink register as was done
for GPIO level register. An upcoming patch will use this.
Change-Id: I6f4749f60a9d569deba4b31f09f07a1321dabf4a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81922
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
ibexpeak has no USB 3 capabilities.
They were kept briefly when its devicetree structure was split from
bd82x6x in commit ab4de83f43 ("sb/intel/ibexpeak: Sever bd82x6x
source dependency") to verify correctness. With that done, they
can go.
Change-Id: I6b847e1532d2e84a7b408a8858c8613b322d0373
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
