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tree: Use boolean for docking_supported

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Change-Id: I25f09457edf4cfb9bec6939de3e56c2ea7965801
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Elyes Haouas 2025-01-16 16:26:30 +01:00
commit 28b4905132
21 changed files with 21 additions and 21 deletions
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2
src/mainboard/asrock/b75pro3-m/devicetree.cb
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@ -26,7 +26,7 @@ chip northbridge/intel/sandybridge
subsystemid 0x1849 0x0152
end
chip southbridge/intel/bd82x6x
register "docking_supported" = "0"
register "docking_supported" = "false"
register "gen1_dec" = "0x000c0291"
register "gen2_dec" = "0x000c0241"
register "gen3_dec" = "0x000c0251"

2
src/mainboard/compulab/intense_pc/devicetree.cb
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@ -24,7 +24,7 @@ chip northbridge/intel/sandybridge # FIXME: check gfx
subsystemid 0x8086 0x7270 inherit
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "docking_supported" = "1"
register "docking_supported" = "true"
register "gen1_dec" = "0x0000164d"
register "gen2_dec" = "0x000c0681"
register "gen3_dec" = "0x000406f1"

2
src/mainboard/dell/e7240/devicetree.cb
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@ -31,7 +31,7 @@ chip northbridge/intel/haswell
device pci 03.0 on end # Mini-HD audio
chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
register "docking_supported" = "1"
register "docking_supported" = "true"
register "alt_gp_smi_en" = "0x00002000"
register "gpe0_en_1" = "0x00000100"
register "gpe0_en_2" = "0x00000080"

2
src/mainboard/dell/snb_ivb_latitude/devicetree.cb
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@ -18,7 +18,7 @@ chip northbridge/intel/sandybridge
end
chip southbridge/intel/bd82x6x # Intel 6/7 Series PCH
register "docking_supported" = "1"
register "docking_supported" = "true"
register "gpi0_routing" = "2"
register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"

2
src/mainboard/dell/xps_8300/devicetree.cb
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@ -5,7 +5,7 @@ chip northbridge/intel/sandybridge
device domain 0x0 on
subsystemid 0x1028 0x04aa inherit
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "docking_supported" = "0"
register "docking_supported" = "false"
register "pcie_port_coalesce" = "1"
register "usb_port_config" = "{

2
src/mainboard/getac/p470/devicetree.cb
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@ -42,7 +42,7 @@ chip northbridge/intel/i945
register "ide_enable_secondary" = "false"
register "c3_latency" = "85"
register "docking_supported" = "1"
register "docking_supported" = "true"
register "p_cnt_throttling_supported" = "true"
register "gen1_dec" = "0x001c02e1"

2
src/mainboard/hp/snb_ivb_desktops/devicetree.cb
View file

@ -15,7 +15,7 @@ chip northbridge/intel/sandybridge
device ref peg60 off end
chip southbridge/intel/bd82x6x # Intel Series 7 PCH
register "docking_supported" = "0"
register "docking_supported" = "false"
register "gen1_dec" = "0x00fc0601"
register "gen2_dec" = "0x00fc0801"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"

2
src/mainboard/hp/snb_ivb_laptops/variants/8560w/overridetree.cb
View file

@ -8,7 +8,7 @@ chip northbridge/intel/sandybridge
device ref igd off end
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "docking_supported" = "0"
register "docking_supported" = "false"
register "gpi6_routing" = "2"
register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }"
# HDD(0), ODD(1), eSATA(4)

2
src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb
View file

@ -12,7 +12,7 @@ chip northbridge/intel/sandybridge
device ref igd off end
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "docking_supported" = "0"
register "docking_supported" = "false"
# mailbox at 0x200/0x201 and PM1 at 0x220
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"

2
src/mainboard/lenovo/l520/devicetree.cb
View file

@ -28,7 +28,7 @@ chip northbridge/intel/sandybridge
device ref igd on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "docking_supported" = "1"
register "docking_supported" = "true"
register "gen1_dec" = "0x007c1611"
register "gen2_dec" = "0x00040069"
register "gen3_dec" = "0x000c0701"

2
src/mainboard/lenovo/s230u/devicetree.cb
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@ -20,7 +20,7 @@ chip northbridge/intel/sandybridge
device ref igd on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "docking_supported" = "1"
register "docking_supported" = "true"
register "gen1_dec" = "0x00000000"
register "gen2_dec" = "0x000c0701"
register "gen3_dec" = "0x000c0069"

2
src/mainboard/lenovo/t410/devicetree.cb
View file

@ -48,7 +48,7 @@ chip northbridge/intel/ironlake
register "gen3_dec" = "0x1c1681" # EC ?
register "gen4_dec" = "0x040069" # ?
register "docking_supported" = "1"
register "docking_supported" = "true"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"

2
src/mainboard/lenovo/t430/devicetree.cb
View file

@ -20,7 +20,7 @@ chip northbridge/intel/sandybridge
subsystemid 0x17aa 0x21f3 inherit
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "docking_supported" = "1"
register "docking_supported" = "true"
register "gen1_dec" = "0x000c15e1"
register "gen2_dec" = "0x007c1601"
register "gen3_dec" = "0x000c06a1"

2
src/mainboard/lenovo/t430s/devicetree.cb
View file

@ -47,7 +47,7 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "true"
register "docking_supported" = "1"
register "docking_supported" = "true"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"

2
src/mainboard/lenovo/t530/devicetree.cb
View file

@ -48,7 +48,7 @@ chip northbridge/intel/sandybridge
register "superspeed_capable_ports" = "0xf"
register "xhci_overcurrent_mapping" = "0x04000201"
register "docking_supported" = "1"
register "docking_supported" = "true"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"

2
src/mainboard/lenovo/x201/devicetree.cb
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@ -48,7 +48,7 @@ chip northbridge/intel/ironlake
register "gen3_dec" = "0x1c1681"
register "gen4_dec" = "0x040069"
register "docking_supported" = "1"
register "docking_supported" = "true"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"

2
src/mainboard/lenovo/x230/variants/x230/overridetree.cb
View file

@ -1,7 +1,7 @@
chip northbridge/intel/sandybridge
device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "docking_supported" = "1"
register "docking_supported" = "true"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "usb_port_config" = "{
{1, 0, 0 }, /* P0 (left, fan side), OC 0 */

2
src/mainboard/msi/ms7707/devicetree.cb
View file

@ -8,7 +8,7 @@ chip northbridge/intel/sandybridge
device ref igd off end # Internal graphics
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "docking_supported" = "0"
register "docking_supported" = "false"
register "gen1_dec" = "0x000c0291"
register "gen2_dec" = "0x000c0a01"
register "pcie_port_coalesce" = "true"

2
src/mainboard/roda/rk886ex/devicetree.cb
View file

@ -37,7 +37,7 @@ chip northbridge/intel/i945
register "gpe0_en" = "0x20800007"
register "c3_latency" = "0x23"
register "docking_supported" = "1"
register "docking_supported" = "true"
register "p_cnt_throttling_supported" = "true"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"

2
src/southbridge/intel/bd82x6x/chip.h
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@ -64,7 +64,7 @@ struct southbridge_intel_bd82x6x_config {
/* Override PCIe ASPM */
uint8_t pcie_aspm[8];
int docking_supported;
bool docking_supported;
bool pcie_hotplug_map[8];

2
src/southbridge/intel/ibexpeak/chip.h
View file

@ -64,7 +64,7 @@ struct southbridge_intel_ibexpeak_config {
/* Override PCIe ASPM */
uint8_t pcie_aspm[8];
int docking_supported;
bool docking_supported;
bool pcie_hotplug_map[8];