i945: Use nullptr instead of NULL

nullptr was introduced in C11 spec and gcc 4.7.

    https://en.cppreference.com/w/cpp/language/nullptr
    https://stackoverflow.com/questions/16256586/how-to-enable-c11-on-later-versions-of-gcc

coreboot switched to GCC 4.7.2 on October 25, 2021, prior to coreboot v4.1.

    https://review.coreboot.org/c/coreboot/+/1609

GCC-13 implemented nullptr constant: https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3042.htm
So use it insted of NULL macro.

Change-Id: I7d47e692a33d739345a81f589d4329a31beeb8c5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83860
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/apple/macbook21/mptable.c

@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);

src/mainboard/getac/p470/mptable.c

@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);

src/mainboard/ibase/mb899/mptable.c

@@ -8,7 +8,7 @@
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
-	struct device *riser = NULL, *firewire = NULL;
+	struct device *riser = nullptr, *firewire = nullptr;
 	int firewire_bus = 0, riser_bus = 0, isa_bus;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
 		printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus);
 	}
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);

src/mainboard/intel/d945gclf/mptable.c

@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);

src/mainboard/kontron/986lcd-m/mainboard.c

@@ -141,7 +141,7 @@ static void mainboard_init(void *chip_info)
 			continue;
 		printk(BIOS_DEBUG, "Disabling Ethernet NIC #%d\n", i);
 		dev = pcidev_on_root(28, i - 1);
-		if (dev == NULL) {
+		if (dev == nullptr) {
 			printk(BIOS_ERR,
 			       "Disabling Ethernet NIC: Cannot find 00:1c.%d!\n",
 			       i - 1);

src/mainboard/kontron/986lcd-m/mptable.c

@@ -7,7 +7,7 @@
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
-	struct device *riser = NULL, *firewire = NULL;
+	struct device *riser = nullptr, *firewire = nullptr;
 	int firewire_bus = 0, riser_bus = 0, isa_bus;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -30,7 +30,7 @@ static void *smp_write_config_table(void *v)
 		riser_bus = riser->downstream->secondary;
 	}
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);

src/mainboard/lenovo/t60/mptable.c

@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);

src/mainboard/lenovo/x60/mptable.c

@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);

src/mainboard/roda/rk886ex/mptable.c

@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	mptable_write_buses(mc, NULL, &isa_bus);
+	mptable_write_buses(mc, nullptr, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
 	u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);

src/northbridge/intel/i945/northbridge.c

@@ -74,14 +74,14 @@ static const char *northbridge_acpi_name(const struct device *dev)
 		return "PCI0";
 
 	if (!is_pci_dev_on_bus(dev, 0))
-		return NULL;
+		return nullptr;
 
 	switch (dev->path.pci.devfn) {
 	case PCI_DEVFN(0, 0):
 		return "MCHC";
 	}
 
-	return NULL;
+	return nullptr;
 }
 
 void northbridge_write_smram(u8 smram)

src/northbridge/intel/i945/raminit.c

@@ -1142,7 +1142,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
 	int i;
 	size_t cum0, cum1, tolud, tom, pci_mmio_size;
 	const struct device *dev;
-	const struct northbridge_intel_i945_config *cfg = NULL;
+	const struct northbridge_intel_i945_config *cfg = nullptr;
 
 	printk(BIOS_DEBUG, "Setting RAM size...\n");
 

src/southbridge/intel/i82801gx/ide.c

@@ -18,7 +18,7 @@ static void ide_init(struct device *dev)
 	const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
 
 	printk(BIOS_DEBUG, "i82801gx_ide: initializing...");
-	if (config == NULL) {
+	if (config == nullptr) {
 		printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in devicetree.cb!\n");
 		// Trying to set somewhat safe defaults instead of bailing out.
 		enable_primary = enable_secondary = 1;

src/southbridge/intel/i82801gx/pcie.c

@@ -138,7 +138,7 @@ static void root_port_commit_config(struct device *dev)
 	int i;
 	bool coalesce = false;
 
-	if (dev->chip_info != NULL) {
+	if (dev->chip_info != nullptr) {
 		const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
 		coalesce = config->pcie_port_coalesce;
 	}
@@ -151,8 +151,8 @@ static void root_port_commit_config(struct device *dev)
 
 		pcie_dev = rpc.ports[i];
 
-		if (pcie_dev == NULL) {
-			printk(BIOS_ERR, "Root Port %d device is NULL?\n", i + 1);
+		if (pcie_dev == nullptr) {
+			printk(BIOS_ERR, "Root Port %d device is nullptr?\n", i + 1);
 			continue;
 		}
 

src/southbridge/intel/i82801gx/sata.c

@@ -76,7 +76,7 @@ static void sata_init(struct device *dev)
 
 	printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n");
 
-	if (config == NULL) {
+	if (config == nullptr) {
 		printk(BIOS_ERR, "i82801gx_sata: error: device not in devicetree.cb!\n");
 		return;
 	}
@@ -130,7 +130,7 @@ static void sata_init(struct device *dev)
 		pci_write_config8(dev, INTR_LN, 0x0a);
 
 		struct resource *ahci_res = probe_resource(dev, PCI_BASE_ADDRESS_5);
-		if (ahci_res != NULL)
+		if (ahci_res != nullptr)
 			/* write AHCI GHC_PI register */
 			write32(res2mmio(ahci_res, 0xc, 0), config->sata_ports_implemented);
 		break;